Stacked assembly including plurality of stacked microelectronic elements

• US 8,513,794 B2
• Filed: 10/17/2011
• Issued: 08/20/2013
• Est. Priority Date: 08/09/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Mohammed, Ilyas
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US13/274,815
• Publication Number:
  US 20120032349A1
• Time in Patent Office: 673 Days
• Field of Search: 438/461
• US Class Current: 257/686
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1029 : the support being a lead frame
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.

Claims

1. A stacked assembly including first and second stacked microelectronic elements, each of said first and second microelectronic elements having a first face, edges extending away from said first face and a plurality of traces extending along said first face towards said edges, wherein said first and second microelectronic elements have first and second different orientations, wherein at least some first traces of said first microelectronic element are electrically isolated from at least some second traces of said second microelectronic element, and

said stacked assembly further includes first and second leads connected to said first and second traces, respectively, said first and second leads extending along said edges.

2. A stacked assembly as claimed in claim 1, wherein said first and second leads extend in parallel paths along at least some aligned edges of said plurality of edges.

3. A stacked assembly as claimed in claim 1, wherein said first faces of said microelectronic elements confront each other.

4. A stacked assembly as claimed in claim 1, further comprising a third microelectronic element stacked in alignment with said first and second microelectronic elements, said third microelectronic element having a third orientation different from said first and second orientations, wherein at least some third traces extend along a first face of said third microelectronic element and are electrically isolated from at least some of said first and said second traces of said first and second microelectronic elements, and

said stacked assembly further includes third leads connected to said third traces, said third leads extending along said edges and being electrically isolated from said first and second leads.

5. A stacked assembly as claimed in claim 4, further comprising a fourth microelectronic element stacked in alignment with said first, second and third microelectronic elements, said fourth microelectronic element having a fourth orientation different from said first, second and third orientations, wherein at least some fourth traces extend along a first face of said fourth microelectronic element and are electrically isolated from at least some of said first, second and third traces, and

said stacked assembly further includes fourth leads connected to said fourth traces, said fourth leads extending along said edges and being electrically isolated from said first, second and third leads.

6. A stacked assembly as claimed in claim 5, wherein said first faces of each of said first, second, third and fourth microelectronic elements has the same width and each said face has the same length.

7. A stacked assembly as claimed in claim 1, wherein each of said first and second microelectronic elements has north-south edges and east-west edges, wherein said traces extend from contacts adjacent to said north-south edges towards said east-west edges.