Charge current reduction for current limited switched power supply

• US 8,513,920 B2
• Filed: 04/01/2009
• Issued: 08/20/2013
• Est. Priority Date: 03/19/2009
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Scaldaferri, Stefano, Wolf, Christian, Marschalkowski, Eric
• Primary Examiner(s): Tso, Edward
• Assistant Examiner(s): HERNANDEZ, MANUEL J
• Application Number:
  US12/384,188
• Publication Number:
  US 20100237845A1
• Time in Patent Office: 1,602 Days
• Field of Search: 320/137, 320139-141, 320/DIG.10
• US Class Current: 320/137
• CPC Class Codes: H02J 2207/20 Charging or discharging characterised by the power electronics converter
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: Y02B 40/00 Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers

Abstract

Circuits and methods for a switched power converter providing charge power for at least one battery and at the same time delivering current to operate an electronic device, wherein the converter is enabled to operate out of current limit mode, for the maximum possible range of system load requirements, have been achieved. The input current of the power converter is measured within each cycle-by-cycle, i.e. within each cycle of an external clock reference and the charge current is reduced if the input current exceeds a defined portion, e.g. 80% of the maximum allowable input current. The power converter may only enter current limited operation after the charge current has been already reduced to zero. Operating out of current limit mode ensures a maximum efficiency of the converter, maximize the current deliverable to a given load and minimizes subharmonics in the output current and voltage, thereby minimizing interference with other system component.

Claims

1. A method allowing switched power converters, providing simultaneously charging power for at least one battery and current to operate an electronic device, to stay out of current limit mode for the maximum possible range of system load requirements, comprising the following steps:

(1) providing a synchronous switched power converter, a means to measure an input current of the switched power converter, and means to control a charge current;

(2) sensing the input current of the switched power converter and perform steps 3 and 5 in parallel;

(3) checking if the input current is higher than a maximum input current limit of the power converter and, if negative, repeat step (3) in a next clock cycle, else go to step (4);

(4) reducing said input current via turning off a high-side switch of said power converter and go to step (3);

(5) checking if the actual input current is higher than a defined portion of the maximum input current limit of the power converter and, if negative, repeat step (5), else go to step (6); and

(6) reduce the charge current and go to step (5).

2. The method of claim 1 wherein said switched power converter is a buck converter.

3. The method of claim 1 wherein said input current is sensed via a voltage drop generated by the input current on an on-resistance of the high side switch.

4. The method of claim 1 wherein said checking if the input current is higher than the maximum input current limit is performed by comparing a voltage drop generated by the input current on an on-resistance of the high side switch with the voltage drop generated by a reference current on an on-resistance of a scaled device matched to the high side switch.

5. The method of claim 1 wherein said checking if the input current is higher than a said defined portion of the maximum input current limit is performed by comparing a voltage drop generated by the input current on an on-resistance of the high side switch with a voltage drop generated by a reference current on an on-resistance of a separated scaled device matched to the high side switch.

6. The method of claim 1 wherein said defined portion of the maximum input current limit is 80%.

7. The method of claim 1 wherein said sensing of the input current is performed cycle-by-cycle in each cycle of an external clock signal.

8. A switched power management unit providing charge power for at least one battery and simultaneously delivering current to operate an electronic device, enabled to stay out of current limit mode for the maximum possible range of system load requirements, comprising:

a switched power converter comprising;

a port for a DC voltage source;

a means to detect if an input current of the power converter exceeds a maximum allowable input current, which is configured to initiate shutting off a high side switch if the input current of the power converter exceeds the maximum allowable input current;

said high side switch;

a means to detect if the input current of the power converter exceeds a defined portion of the maximum allowable input current; and

a digital control circuitry controlling a charger, wherein said charger reduces a charge current if the input current of the power converter is higher than the defined portion of the maximum allowable input current; and

said controllable charger for said at least one battery;

wherein said means to detect if the input current of the power converter exceeds the maximum allowable input current and said means to detect if the input current of the power converter exceeds the defined portion of the maximum allowable input current comprises two comparators, a first comparator reducing directly the input current of the power converter via turning off the high side switch, and a second comparator reducing indirectly the input current of the power converter via controlling a digital circuit which in turn reduces a fraction of a current load.

9. The system of claim 8 wherein said switched power converter is a buck converter.

10. The system of claim 8 wherein said defined portion of a maximum allowable input current is 80%.

11. The system of claim 8 wherein said means to sense the input current comprises sensing a voltage drop produced by the input current on an on-resistance of a transistor.

12. The system of claim 8 wherein said means to detect if the input current exceeds the maximum allowable input current and the defined portion of the maximum allowable input current comprises two transistors in series matching a high side buck converter switch, a current reference forced through them and generating two voltage references on their on-resistance, corresponding to the maximum allowable input current and to the defined portion of the maximum allowable input current.

13. A switched power management unit providing charge power for at least one battery and simultaneously delivering current to operate an electronic device, enabled to stay out of current limit mode for the maximum possible range of system load requirements, comprising:

a switched power converter comprising;

a port for a DC voltage source;

an inductor, wherein a first terminal of the inductor is connected to a second terminal of a main switching means and to a first terminal of a rectifying switching means and a second terminal of the inductor is connected to an output port of the switched power converter, wherein the output port is connected to said electronic device and to a controllable charger of batteries;

a capacitor being connected between said output port and ground;

said main switching means, wherein the first terminal of said main switching means is connected to said port for said DC voltage source;

said rectifying switching means, wherein a second terminal of said rectifying switching means is connected to ground;

a drive logic circuitry controlling said main switching means and said rectifying switching means, receiving inputs from a SR latch;

a means of current measurement monitoring an input current of the power management unit provided by said DC voltage source;

said SR latch, wherein an output of the SR latch is connected to said drive logic circuitry and a first input of the SR latch is connected to an internal clock and a second input of the SR latch is connected to an output of an OR-gate;

said OR gate, wherein a first input of the OR gate is connected to an output of a first comparing means and a second input is connected to an output of a second comparing means;

said first comparing means, wherein a first input of the first comparing means is a voltage proportional to a current through said inductor and a second input of the first comparing means is an output of an amplifier;

said second comparing means wherein a first input of the second comparing means is a voltage proportional to the input current of the power management unit provided by said DC voltage source and a second input is a first reference voltage proportional to a maximum allowable input current of the power management unit;

said amplifier, wherein a first input of the amplifier is an output voltage of the switched power management unit and a second input is a second reference voltage;

a third comparing means, wherein a first input of the third comparing means is a voltage proportional to the input current of the power management unit and a second input of the third comparing means is a third reference voltage being proportional to a defined portion of the maximum allowable input current of the power management unit and an output of the third comparing means is connected to a digital control circuitry; and

said digital control circuitry, wherein an output of said digital control circuitry is controlling said charger in a way that a charging current is reduced if the input current of the power management unit is higher than the defined portion of the maximum allowable input current of the power management unit, and

said controllable charger.

14. The system of claim 13 wherein said switched power converter is a buck converter.

15. The system of claim 13 wherein said defined portion of the maximum allowable input current is 80%.

16. The system of claim 13 wherein said main switching means is a transistor.

17. The system of claim 16 wherein a drain voltage of said transistor is compared to drain voltages of two scaled transistors in series matching said transistor, wherein a drain of a first transistor is connected to a source of a second transistor and a drain of the second transistor is connected to a current source and gates of both transistors are connected to each other and to said drive logic circuitry, and wherein a voltage on said drain of said second transistor corresponds to the maximum allowable input current of the power management unit and a voltage of the source of said second transistor corresponds to the defined portion of the maximum allowable input current of the power management unit.