Semiconductor device and method of manufacturing the same, and electronic apparatus

• US 8,514,308 B2
• Filed: 12/08/2010
• Issued: 08/20/2013
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Itonaga, Kazuichiro, Horiike, Machiko
• Primary Examiner(s): Ho, Tuan
• Assistant Examiner(s): Nazrul, Shahbaz
• Application Number:
  US12/962,854
• Publication Number:
  US 20110157445A1
• Time in Patent Office: 986 Days
• Field of Search: 348/294, 348/340
• US Class Current: 348/294
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/24147 the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14647 Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H04N 25/76 : Addressed sensors, e.g. MOS or CMOS sensors

Abstract

A semiconductor device comprising a first semiconductor section including a first wiring layer at one side thereof, a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other, a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.

Claims

1. A semiconductor device comprising:

a first semiconductor section (1) including a first wiring layer at one side thereof and (2) having a circuit region and a pixel region;

a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other;

an insulation layer and a planarizing layer on another side of the first semiconductor section in that order, the planarizing layer having a concavity in an outer surface thereof, the concavity being outside of the circuit and pixel regions; and

a conductive material extending from the concavity and through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication.

2. The semiconductor device of claim 1 wherein, the first semiconductor section and the second semiconductor section are secured by plasma bonding.

3. The semiconductor device of claim 1 wherein, the first semiconductor section and the second semiconductor section are secured by an adhesive.

4. The semiconductor device of claim 1 wherein, the circuit region is between the pixel region and the concavity.

5. The semiconductor device of claim 4, wherein the conductive material is formed in the concavity in the planarizing layer.

6. The semiconductor device of claim 5, further comprising a light shielding film over the first semiconductor section in the control region of the semiconductor device.

7. A method of manufacturing a semiconductor device including the steps of:

providing a first semiconductor section (1) including a first wiring layer at one side thereof and (2) having a circuit region and a pixel region;

providing a second semiconductor section including a second wiring layer at one side thereof;

bonding the first semiconductor section to the second semiconductor section with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other;

forming an insulation layer and a planarizing layer on another side of the first semiconductor section in that order, the planarizing layer having a concavity in an outer surface thereof, the concavity being outside of the circuit and pixel regions; and

providing a conductive material extending from the concavity and through the first semiconductor section to the second wiring layer of the second semiconductor section so that the first and second wiring layers are in electrical communication.

8. The method of claim 7 wherein, the first semiconductor section and the second semiconductor section are secured by plasma bonding.

9. The method of claim 7 wherein, the first semiconductor section and the second semiconductor section are secured by an adhesive.

10. The method of claim 7 wherein, the circuit region is between the pixel region and the concavity in the planarizing layer.

11. The method of claim 10, wherein the conductive material is formed in the concavity of the planarizing layer.

12. The method of claim 11, further comprising the step of forming a light shielding film over the first semiconductor section in the control region of the semiconductor device.

13. A semiconductor device comprising:

a first semiconductor section (1) including a first wiring layer on one side and a device layer on the opposite side of the first wiring layer and (2) having a circuit region and a pixel region;

a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other;

an insulation layer and a planarizing layer on another side of the first semiconductor section in that order, the planarizing layer having a concavity in an outer surface thereof, the concavity being outside of the circuit and pixel regions;

a first conductive material which extends from the concavity and through the device layer of the first semiconductor section to a connection point in the first wiring layer of the first semiconductor section; and

a second conductive material which extends from the concavity and through the first semiconductor section to a connection point in the second wiring layer of the second semiconductor section, the first and second conductive materials being connected within the concavity such that the first and second wiring layers are in electrical communication.

14. The semiconductor device of claim 13 wherein, the first semiconductor section and the second semiconductor section are secured by plasma bonding.

15. The semiconductor device of claim 13 wherein, the first semiconductor section and the second semiconductor section are secured by an adhesive.

16. The semiconductor device of claim 13 wherein, the circuit region is between the pixel region and the concavity.

17. The semiconductor device of claim 16, wherein the first and second conductive materials are formed in the concavity of the planarizing layer.

18. The semiconductor device of claim 17, further comprising a light shielding film formed over the first semiconductor section in the circuit region of the semiconductor device.

19. A method of manufacturing a semiconductor device including the steps of:

providing a first semiconductor section (1) including a first wiring layer on one side and a device layer on the opposite side of the first wiring layer and (2) having a circuit region and a pixel region;

providing a second semiconductor section including a second wiring layer at one side thereof;

bonding the first semiconductor section to the second semiconductor section with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other;

forming an insulation layer and a planarizing layer on another side of the first semiconductor section in that order, the planarizing layer having a concavity in an outer surface thereof, the concavity being outside of the circuit and pixel regions;

providing a first conductive material which extends from the concavity and through the device layer of the first semiconductor section to a connection point in the first wiring layer of the first semiconductor section; and

providing a second conductive material which extends from the concavity and through the first semiconductor section to a connection point in the second wiring layer of the second semiconductor section, the first and second conductive materials being connected within the concavity such that the first and second wiring layers are in electrical communication.

20. The method of claim 19 wherein, the first semiconductor section and the second semiconductor section are secured by plasma bonding.

21. The method of claim 19 wherein, the first semiconductor section and the second semiconductor section are secured by an adhesive.

22. The method of claim 19 wherein, the circuit region is between the pixel region and the concavity.

23. The method of claim 22, wherein the first and second conductive materials are formed in the concavity.

24. The semiconductor device of claim 23, further comprising a light shielding film formed over the first semiconductor section in the control region of the semiconductor device.

25. An electronic apparatus including:

an optical unit; and

an imaging unit including

(a) a first semiconductor section (1) including a first wiring layer and a device layer on the first wiring layer and (2) having a circuit region and a pixel region,

(b) a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other,

(c) an insulation layer and a planarizing layer on another side of the first semiconductor section in that order, the planarizing layer having a concavity in an outer surface thereof, the concavity being outside of the circuit and pixel regions,

(d) a first conductive material which extends from the concavity and through the device layer of the first semiconductor section to a connection point in the first wiring layer of the first semiconductor section, and

(e) a second conductive material which extends through the first semiconductor section to a connection point in the second wiring layer of the second semiconductor section, the first and second conductive materials being connected within the concavity such that the first and second wiring layers are in electrical communication.

26. The apparatus of claim 25 further comprising a shutter device between the optical unit and the imaging unit.

27. A semiconductor device comprising:

a first semiconductor section including a first wiring layer at one side thereof;

a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other;

a plurality of first conductive materials which extend through the device layer of the first semiconductor section to a connection point in the first wiring layer of the first semiconductor section, and

a plurality of second conductive materials which extend through the first semiconductor section to a connection point in the second wiring layer of the second semiconductor section,

wherein

the first and second conductive materials are arranged alternately in a first direction across the first semiconductor section, and

the first and second conductive materials are arranged alternately a second direction across the first semiconductor section, the first and second directions being orthogonal to each other.