Bipolar select device for resistive sense memory

• US 8,514,608 B2
• Filed: 03/16/2012
• Issued: 08/20/2013
• Est. Priority Date: 07/07/2009
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Khoury, Maroun Georges
• Primary Examiner(s): Le, Toan
• Assistant Examiner(s): PHAM, HAI Q
• Application Number:
  US13/422,219
• Publication Number:
  US 20120175718A1
• Time in Patent Office: 522 Days
• Field of Search: 365/148, 365/189.16, 365/242, 365/17, 257/2, 257/241, 257/E29.323, 257/421
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors

Abstract

A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate, a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, an emitter contact layer disposed in a second side of the semiconductor substrate, and a base layer separating the plurality of collector contacts from the emitter contact layer. Each collector contact is electrically isolated from each other. A resistive sense memory cells is electrically coupled to each collector contacts and a bit line. The base layer and the emitter contact layer provide an electrical path for the plurality of collector contacts.

Claims

1. A spin transfer torque memory apparatus comprising:

a bipolar select device comprising;

a semiconductor substrate having a first side and an opposing second side;

a plurality of collector contacts disposed in the first side of the of the semiconductor substrate, wherein each collector contact is electrically isolated from each other;

an emitter contact layer disposed in the second side of the semiconductor substrate, the emitter contact layer being electrically coupled to a source line; and

a base layer disposed between the plurality of collector contacts and the emitter contact layer, the base layer being electrically coupled to a word line; and

a plurality of spin transfer torque memory cells, wherein one of the plurality of spin transfer torque memory cells is electrically coupled to one of the plurality of collector contacts and a bit line associated with the one of the plurality of spin transfer torque memory cells, wherein the base layer and the emitter contact layer provides an electrical path for the plurality of collector contacts.

2. A spin transfer torque memory apparatus according to claim 1, wherein the collector contacts and the emitter contact layer have N type conductivity and the base layer has P type conductivity.

3. A spin transfer torque memory apparatus according to claim 1, wherein the collector contacts and the emitter contact layer have P type conductivity and the base layer has N type conductivity.

4. A spin transfer torque memory apparatus according to claim 1, wherein the spin transfer torque memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

5. A spin transfer torque memory apparatus according to claim 1, wherein the word line and the source line provide an electrical path to the plurality of spin transfer torque memory cells by selecting a desired bit line.

6. A spin transfer torque memory apparatus according to claim 1, further comprising a plurality of bipolar select devices, wherein each bipolar select device forms a row of a memory array.

7. A spin transfer torque memory apparatus according to claim 6, wherein each bipolar select device is electrically isolated from each other.

8. A spin transfer torque memory apparatus according to claim 6, wherein each bipolar select device is electrically isolated from each other by deep trench isolation.

9. A spin transfer torque memory apparatus according to claim 1, wherein the emitter contact layer extends along a length of the bipolar select device and the plurality of collector contacts are disposed along the length of the bipolar select device.

10. A spin transfer torque memory array, comprising:

a plurality of bipolar select devices, each bipolar select device forming a row of a memory array, each bipolar select device comprising;

a semiconductor substrate;

a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, wherein each collector contact is electrically isolated from each other;

an emitter contact layer disposed in a second side of the semiconductor substrate, the second side opposing the first side, the emitter contact layer being electrically coupled to a source line; and

a base layer separating the plurality of collector contacts from the emitter contact layer, the base layer being electrically coupled to a word line; and

a plurality of spin transfer torque memory cells, wherein one of the plurality of spin transfer torque memory cells is electrically coupled to one of the plurality of collector contacts and a bit line associated with the one of the plurality of spin transfer torque memory cells, wherein the base layer of each bipolar select device and the emitter contact layer of each bipolar select device provides an electrical path for the plurality of collector contacts for the bipolar select device.

11. A spin transfer torque memory array according to claim 10, wherein each bipolar select device is electrically isolated from each other.

12. A spin transfer torque memory array according to claim 10, wherein each bipolar select device is electrically isolated from each other by deep trench isolation.

13. A spin transfer torque memory array according to claim 10, wherein the emitter contact layer extends along a length of the bipolar select device and the plurality of collector contacts are disposed along the length of the bipolar select device.

14. A spin transfer torque memory array according to claim 10, wherein the collector contacts and the emitter contact layer have N type conductivity and the base layer has P type conductivity.

15. A spin transfer torque memory array according to claim 10, wherein the collector contacts and the emitter contact layer have P type conductivity and the base layer has N type conductivity.

16. A spin transfer torque memory array according to claim 10, wherein the spin transfer torque memory cells comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

17. A spin transfer torque memory array according to claim 10, wherein the word line and the source line provide an electrical path to the plurality of spin transfer torque memory cells by selecting a desired bit line.

18. A method, comprising:

writing a first data state to a plurality of spin transfer torque memory cells by applying a forward bias across an emitter contact layer of a bipolar select device and selected bit lines electrically coupled to the plurality of spin transfer torque memory cells to be written to, wherein the bipolar select device comprises;

a semiconductor substrate;

a plurality of collector contacts disposed in a first side of the of the semiconductor substrate, wherein each collector contact is electrically isolated from each other and each collector is electrically coupled to a spin transfer torque memory cell;

the emitter contact layer disposed in a second side of the semiconductor substrate, the second side opposing the first side, the emitter contact layer being electrically coupled to a source line; and

a base layer separating the plurality of collector contacts from the emitter contact, the base layer being electrically coupled to a word line.

19. A method according to claim 18, further comprising writing a second data state to a plurality of spin transfer torque memory cells by applying a reverse bias across an emitter contact layer of a bipolar select device and selected bit lines electrically coupled to the plurality of spin transfer torque memory cells to be written to.

20. A method according to claim 18, wherein the writing step comprises applying a spin polarized current thought the spin transfer torque memory cells.