Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 8,514,622 B2
• Filed: 10/04/2010
• Issued: 08/20/2013
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US12/897,528
• Publication Number:
  US 20110032756A1
• Time in Patent Office: 1,051 Days
• Field of Search: 365/185.05, 365/185.17, 365/182
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. An integrated circuit comprising:

a link or string of semiconductor memory cells, wherein each said memory cell comprises a floating body region for storing data; and

said link or string comprises at least one contact configured to electrically connect said memory cells to at least one control line, wherein the number of contacts is the same as or less than the number of said memory cells.

2. The integrated circuit of claim 1, wherein said number of contacts is less than said number of memory cells.

3. The integrated circuit of claim 1, where said semiconductor memory cells are connected in series.

4. The integrated circuit of claim 1, where said semiconductor memory cells are connected in parallel.

5. The integrated circuit of claim 1, where said integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.

6. The integrated circuit of claim 1, where said integrated circuit is fabricated on a bulk silicon substrate.

7. The integrated circuit of claim 1, where said number of contacts is two.

8. The integrated circuit of claim 1, wherein said memory cells further comprise first and second conductive regions interfacing with said floating body region.

9. The integrated circuit of claim 8, wherein said first and second conductive regions are shared by adjacent ones of said memory cells for each said memory cell having said adjacent memory cells.

10. The integrated circuit of claim 1, wherein each said memory cell further comprises first, second, and third conductive regions interfacing with said floating body region.

11. The integrated circuit of claim 1, wherein each said memory cell further comprises a gate insulated from said floating body region.

12. The integrated circuit of claim 1, wherein at least one of said memory cells is a contactless memory cell.

13. The integrated circuit of claim 12, wherein a majority of said memory cells are contactless memory cells.

14. The integrated circuit of claim 1, wherein said memory cells store multi-bit data.

15. An integrated circuit comprising:

a plurality of contactless semiconductor memory cells, each said semiconductor memory cell comprising;

a floating body region for storing data;

first and second conductive regions interfacing with the floating body region;

a gate; and

an insulating region insulating said gate from said floating body region.

16. The integrated circuit of claim 15, wherein said contactless memory cells are connected in series.

17. The integrated circuit of claim 15, wherein said contactless memory cells are connected in parallel.

18. The integrated circuit of claim 15, wherein said integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.

19. The integrated circuit of claim 15, wherein said integrated circuit is fabricated on a bulk silicon substrate.

20. The integrated circuit of claim 15, wherein each said contactless memory cell comprises a third conductive region interfacing with the floating body region.

21. The integrated circuit of claim 15, wherein said integrated circuit comprises at least one semiconductor memory cell having at least one contact, a total number of said contacts being less than a total number of memory cells that includes a total number of said memory cells having at least one contact and a total number of said contactless memory cells.

22. The integrated circuit of claim 15, wherein said memory cells store multi-bit data.

23. An integrated circuit comprising:

a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising;

a floating body region for storing data;

first and second conductive regions interfacing with said floating body region;

a gate; and

an insulating region insulating the gate and the floating body region.

24. The integrated circuit of claim 23, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

25. The integrated circuit of claim 23, wherein said integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.

26. The integrated circuit of claim 23, wherein said integrated circuit is fabricated on a bulk silicon substrate.

27. The integrated circuit of claim 23, wherein said integrated circuit comprises a number of contacts, said number of contacts being less than or equal to a number of said memory cells.

28. The integrated circuit of claim 23, wherein said memory cells each further comprise a third conductive region interfacing with said floating body region.

29. The integrated circuit of claim 23, wherein said memory cells store multi-bit data.

30. An integrated circuit comprising:

a plurality of semiconductor memory cells connected in parallel, each said semiconductor memory cell comprising;

a floating body region for storing data;

a conductive region interfacing with the floating body region;

a gate; and

an insulating region insulating said gate from said floating substrate region;

wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.

31. The integrated circuit of claim 30, wherein a majority of said semiconductor memory cells are contactless semiconductor memory cells.

32. The integrated circuit of claim 30, wherein said integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.

33. The integrated circuit of claim 30, wherein said integrated circuit is fabricated on a bulk silicon substrate.

34. The integrated circuit of claim 30, wherein said integrated circuit comprises a number of contacts, said number being less than or equal to a number of said memory cells.

35. The integrated circuit of claim 30, wherein at least one of said memory cells fluffier comprises a second conductive region interfacing with said floating body region.

36. The integrated circuit of claim 30, wherein said memory cells each further comprise second and third conductive regions interfacing with said floating body region.

37. The integrated circuit of claim 30, wherein said memory cells store multi-bit data.

38. An integrated circuit comprising:

a plurality of contactless semiconductor memory cells connected in parallel, each said semiconductor memory cell comprising;

a floating body region for storing data;

first and second conductive regions interfacing with the floating body region;

a gate; and

an insulating region insulating the gate and the floating body region.

39. The integrated circuit of claim 38, where said integrated circuit is fabricated on a silicon-on-insulator (SOI) substrate.

40. The integrated circuit of claim 38, where said integrated circuit is fabricated on a bulk silicon substrate.

41. The integrated circuit of claim 38, wherein each said contactless memory cell comprises a third conductive region interfacing with the floating body region.

42. The integrated circuit of claim 38, wherein the number of contacts is the same or less than the number of said memory cells.

43. The integrated circuit of claim 38, wherein said memory cells store multi-bit data.

44. An integrated circuit comprising:

a memory string or link comprising a set of contactless semiconductor memory cells; and

a first contact contacting a semiconductor transistor forming part of said string or link; and

wherein said contactless semiconductor memory cells are accessible via said first contact.

45. The integrated circuit of claim 44, further comprising:

a second contact contacting a second semiconductor transistor forming part of said string or link;

wherein said contactless semiconductor memory cells are accessible via said second contact.

46. The integrated circuit of claim 44, wherein said contactless semiconductor memory cells and said transistors are connected in series.

47. The integrated circuit of claim 44,

wherein said memory string or link comprises a first memory string or link and said set comprises a first set, said integrated circuit further comprising:

a second memory string or link comprising a second set of contactless semiconductor memory cells; and

a second contact contacting a second semiconductor transistor forming part of said second memory string or link;

wherein said second set of contactless semiconductor memory cells are accessible via said second contact.

48. The integrated circuit of claim 45,

wherein said memory string or link comprises a first memory string and said set comprises a first set, said integrated circuit further comprising:

a second memory string comprising a second set of contactless semiconductor memory cells;

a third contact contacting a third semiconductor transistor forming part of said second memory string or link; and

a fourth contact contacting a fourth semiconductor transistor forming part of said second memory string or link;

wherein said second set of contactless semiconductor memory cells are accessible via said third and fourth contacts;

wherein said first set of contactless semiconductor memory cells, said first semiconductor transistor and said second semiconductor transistor are connected in series, and

wherein said second set of contactless semiconductor memory cells, said third semiconductor transistor and said fourth semiconductor transistor are connected in series in said second string.

49. The integrated circuit of claim 48, further comprising

a first terminal connected to said first contact and said third contact;

a second terminal connected to said second contact; and

a third terminal connected to said fourth contact.

50. The integrated circuit of claim 44, wherein said semiconductor memory cells comprise substantially planar semiconductor memory cells.

51. The integrated circuit of claim 44, wherein said semiconductor memory cells comprise fin-type, three-dimensional semiconductor memory cells.

52. The integrated circuit of claim 47, wherein said first set of contactless semiconductor memory cells are aligned side-by side of said second set of contactless semiconductor memory cells;

and

wherein said first string comprises a first set of insulation portions that insulate adjacent memory cells in said first string, and a second set of insulation portions that insulate said memory cells in said first string from adjacent memory cells in said second string; and

wherein said second string comprises a third set of insulation portions that insulate adjacent memory cells in said second siring, and said second set of insulation portions insulate said memory cells in said second siring from adjacent memory cells in said first siring.

53. The integrated circuit of claim 45, wherein said first and second contacts are located at first and second ends of said memory siring.

54. The integrated circuit of claim 44, wherein each said semiconductor memory cell comprises:

a floating body region for storing data;

first and second conductive regions interfacing with said floating body region;

a gate;

an insulating region insulating said gate from said floating body region; and

a word line terminal electrically connected to said gate.