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Method of maintaining the state of semiconductor memory having electrically floating body transistor

  • US 8,514,623 B2
  • Filed: 05/22/2012
  • Issued: 08/20/2013
  • Est. Priority Date: 11/29/2007
  • Status: Active Grant
First Claim
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1. A semiconductor memory cell comprising:

  • a floating body region configured to be charged to a level indicative of a state of the memory cell;

    a first region in electrical contact with said floating body region, located at a surface of said floating body region; and

    a second region in electrical contact with said floating body region, located below said floating body region, configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;

    wherein an amount of charge flow resulting from injecting charge into or extracting charge out of said floating body is determined by the state of the memory cell stored in said floating body region.

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