Method of maintaining the state of semiconductor memory having electrically floating body transistor

• US 8,514,623 B2
• Filed: 05/22/2012
• Issued: 08/20/2013
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/478,014
• Publication Number:
  US 20120230123A1
• Time in Patent Office: 455 Days
• Field of Search: 365/185.05, 365/185.18
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. A semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region, located at a surface of said floating body region; and

a second region in electrical contact with said floating body region, located below said floating body region, configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;

wherein an amount of charge flow resulting from injecting charge into or extracting charge out of said floating body is determined by the state of the memory cell stored in said floating body region.

2. The semiconductor memory cell of claim 1, wherein said floating body has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

said first region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said second region has said second conductivity type.

3. The semiconductor memory cell of claim 1, further comprising a third region having a second conductivity type, said third region being spaced apart from said first region.

4. The semiconductor memory cell of claim 1, further comprising a gate region above said floating body.

5. The semiconductor memory cell of claim 1, further comprising:

a terminal connected to said first region; and

a back bias terminal connected to said second region.

6. The semiconductor memory cell of claim 1, wherein applying a voltage to said second region offsets charge leakage out of said floating body.

7. The semiconductor memory cell of claim 6, wherein said voltage applied to said second region is a constant positive voltage bias.

8. The semiconductor memory cell of claim 6, wherein said voltage applied to said second region is a periodic pulse of positive voltage.

9. A semiconductor memory cell comprising:

a floating body region;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region;

a gate positioned between said first and second regions; and

a back-bias region;

wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels.

10. The memory cell of claim 9, wherein said voltage applied to said back-bias region is a constant positive voltage bias.

11. The memory cell of claim 9, wherein said voltage applied to said back-bias region is a periodic pulse of positive voltage.

12. The memory cell of claim 9, wherein a maximum potential that can be stored in said floating body is increased by said applying back bias to the cell, resulting in a relatively larger memory window.

13. A semiconductor memory array comprising:

a plurality of said memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region;

a second region in electrical contact with said floating body region and spaced apart from said first region; and

a gate positioned between said first and second regions; and

wherein a back-bias region is commonly connected to at least two of said memory cells, configured to inject charge into or extract charge out of said floating body region of each of said memory cells connected thereto, to maintain said state of the memory cells in parallel.

14. The semiconductor memory array of claim 13 wherein each said first region has a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said floating body region has a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type;

each said second region has said first conductivity type; and

said back bias region comprises a substrate having said first conductivity type.

15. The semiconductor memory array of claim 13, wherein said back-bias region is commonly connected to all of said memory cells in said memory array.

16. The semiconductor memory array of claim 13, wherein said back-bias region is segmented to allow independent control of bias applied to a selected portion of said memory array.

17. The semiconductor array of claim 13, wherein application of voltage to said back bias region results maintains the current states of each said memory cell connected thereto.

18. The semiconductor array of claim 17, wherein said application of voltage is applied as a constant positive voltage bias.

19. The semiconductor array of claim 17, wherein said application of voltage is applied as a periodic pulse of positive voltage bias.

20. The semiconductor array of claim 17, wherein a maximum potential that can be held by any one of said memory cells connected to said back bias region is increased by said application of voltage to said back bias region, resulting in a relatively larger memory window.