Frequency correction of a programmable frequency oscillator by propagation delay compensation

• US 8,515,361 B2
• Filed: 08/04/2011
• Issued: 08/20/2013
• Est. Priority Date: 04/20/2010
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Levesque, Chris, Berchtold, Jean-Christophe, Colles, Joseph Hubert
• Primary Examiner(s): Nguyen, Duc M
• Application Number:
  US13/198,074
• Publication Number:
  US 20120207252A1
• Time in Patent Office: 747 Days
• Field of Search: 455/75, 455/76, 455/164.1, 455/165.1, 455/192.1, 455/196.1, 455/255, 455/258, 455/259
• US Class Current: 455/75
• CPC Class Codes: H02M 1/0064 Magnetic structures combining different functions, e.g. storage, filtering or transformation
• CPC Class Codes: H02M 1/008 Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03C 3/09 Modifications of modulator for regulating the mean frequency
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/171 A filter circuit coupled to the output of an amplifier
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/27 A biasing circuit node being switched in an amplifier circuit
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/414 A switch being coupled in the output circuit of an amplifier to switch the output on/off
• CPC Class Codes: H03F 2200/417 A switch coupled in the output circuit of an amplifier being controlled by a circuit
• CPC Class Codes: H03F 2200/421 Multiple switches coupled in the output circuit of an amplifier are controlled by a circuit
• CPC Class Codes: H03F 2200/426 : the amplifier comprising circuitry for protection against overload
• CPC Class Codes: H03F 2200/429 : Two or more amplifiers or one amplifier with filters for different frequency bands are coupled in parallel at the input or output
• CPC Class Codes: H03F 2200/504 : the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
• CPC Class Codes: H03F 2200/555 : A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2203/21106 : An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 : Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 2203/21145 : Output signals are combined by switching a plurality of paralleled power amplifiers to a common output
• CPC Class Codes: H03F 2203/21157 : A filter circuit being added at the output of a power amplifier stage
• CPC Class Codes: H03F 2203/21175 : An output signal of a power amplifier being on/off switched
• CPC Class Codes: H03F 2203/7209 : the gated amplifier being switched from a first band to a second band
• CPC Class Codes: H03F 2203/7221 : the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7236 : the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/189 : High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03F 3/72 : Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03G 3/3042 : in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03J 7/04 : where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
• CPC Class Codes: H04B 1/405 : with multiple discrete channels

Abstract

A first programmable frequency oscillator, which includes a first ramp comparator and programmable signal generation circuitry is disclosed. The programmable signal generation circuitry provides a ramping signal, which has a first frequency, based on a desired first frequency. The first ramp comparator receives the ramping signal and provides a first ramp comparator output signal based on the ramping signal. The first ramp comparator output signal is fed back to the programmable signal generation circuitry, such that the ramping signal is based on the desired first frequency and the first ramp comparator output signal. However, the first ramp comparator has a first propagation delay, which introduces a frequency error into the programmable frequency oscillator. Therefore, the first frequency is not proportional to one or more slopes of the ramping signal. As a result, the programmable signal generation circuitry compensates for the frequency error based on the desired first frequency.

Claims

1. Circuitry comprising:

a first ramp comparator having a first propagation delay and adapted to;

receive a ramping signal having a first frequency based on a desired first frequency; and

provide a first ramp comparator output signal based on the ramping signal; and

programmable signal generation circuitry adapted to;

provide the ramping signal based on the desired first frequency and the first ramp comparator output signal; and

compensate for the first propagation delay based on the desired first frequency,

wherein the first ramp comparator and the programmable signal generation circuitry provide a first programmable frequency oscillator.

2. The circuitry of claim 1 wherein the compensation for the first propagation delay frequency corrects the first frequency.

3. The circuitry of claim 1 wherein:

the programmable signal generation circuitry is further adapted to provide a first comparator reference signal; and

the first ramp comparator is further adapted to receive the first comparator reference signal, such that the first ramp comparator output signal is further based on a difference between the ramping signal and the first comparator reference signal.

4. The circuitry of claim 3 wherein the programmable signal generation circuitry is further adapted to adjust the first comparator reference signal to compensate for the first propagation delay based on the desired first frequency.

5. The circuitry of claim 4 wherein the programmable signal generation circuitry comprises a first reference digital-to-analog converter adapted to provide the first comparator reference signal.

6. The circuitry of claim 1 wherein the programmable signal generation circuitry is further adapted to adjust a first slope of the ramping signal to compensate for the first propagation delay based on the desired first frequency.

7. The circuitry of claim 1 wherein the ramping signal is a sawtooth signal.

8. The circuitry of claim 1 wherein the programmable signal generation circuitry comprises a first ramp current digital-to-analog converter, a capacitor discharge circuit, and a ramp capacitive element, such that the first ramp current digital-to-analog converter, the capacitor discharge circuit, and the ramp capacitive element are adapted to provide the ramping signal.

9. The circuitry of claim 1 further comprising a second ramp comparator having a second propagation delay, wherein:

the second ramp comparator is adapted to;

receive the ramping signal; and

provide a second ramp comparator output signal based on the ramping signal; and

the programmable signal generation circuitry is further adapted to;

provide the ramping signal further based on the second ramp comparator output signal; and

compensate for the second propagation delay based on the desired first frequency.

10. The circuitry of claim 9 wherein:

the programmable signal generation circuitry is further adapted to provide a second comparator reference signal; and

the second ramp comparator is further adapted to receive the second comparator reference signal, such that the second ramp comparator output signal is further based on a difference between the ramping signal and the second comparator reference signal.

11. The circuitry of claim 10 wherein the programmable signal generation circuitry is further adapted to adjust the second comparator reference signal to compensate for the second propagation delay based on the desired first frequency.

12. The circuitry of claim 11 wherein the programmable signal generation circuitry comprises a first reference digital-to-analog converter adapted to provide the first comparator reference signal and the programmable signal generation circuitry further comprises a second reference digital-to-analog converter adapted to provide the second comparator reference signal.

13. The circuitry of claim 9 wherein the programmable signal generation circuitry is further adapted to:

adjust a first slope of the ramping signal to compensate for the first propagation delay based on the desired first frequency; and

adjust a second slope of the ramping signal to compensate for the second propagation delay based on the desired first frequency.

14. The circuitry of claim 9 wherein the ramping signal is a triangular signal.

15. The circuitry of claim 1 wherein the programmable signal generation circuitry comprises a first ramp current digital-to-analog converter, a second ramp current digital-to-analog converter, and a ramp capacitive element, such that the first ramp current digital-to-analog converter, the second ramp current digital-to-analog converter, and the ramp capacitive element are adapted to provide the ramping signal.

16. The circuitry of claim 1 wherein the ramping signal is a first oscillator output signal.

17. The circuitry of claim 1 wherein the first ramp comparator output signal is a first oscillator output signal.

18. The circuitry of claim 1 further comprising control circuitry adapted to select the desired first frequency.

19. The circuitry of claim 1 wherein the programmable signal generation circuitry is further adapted to:

frequency dither the ramping signal, such that the ramping signal has a plurality of frequencies based on a plurality of desired frequencies; and

compensate for the first propagation delay based on the plurality of desired frequencies,

wherein the plurality of frequencies includes the first frequency and the plurality of desired frequencies includes the desired first frequency.

20. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising;

a first non-quadrature PA path having a first single-ended output; and

a first quadrature PA path coupled between the first non-quadrature PA path and an antenna port, such that the first quadrature PA path has a first single-ended input, which is coupled to the first single-ended output; and

a second RF PA comprising a second quadrature PA path coupled to the antenna port,

wherein the antenna port is configured to be coupled to an antenna.

21. The circuitry of claim 1 further comprising:

a first multi-mode multi-band quadrature radio frequency (RF) power amplifier (PA) coupled to multi-mode multi-band alpha switching circuitry via a single alpha PA output; and

the multi-mode multi-band alpha switching circuitry having;

a first alpha non-linear mode output associated with a first non-linear mode RF communications band; and

a plurality of alpha linear mode outputs, such that each of the plurality of alpha linear mode outputs is associated with a corresponding one of a first plurality of linear mode RF communications bands.

22. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) comprising a first final stage having a first final bias input, such that bias of the first final stage is via the first final bias input;

PA control circuitry;

a PA-digital communications interface (DCI) coupled between a digital communications bus and the PA control circuitry; and

a final stage current digital-to-analog converter (IDAC) coupled between the PA control circuitry and the first final bias input.

23. The circuitry of claim 1 further comprising:

a first radio frequency (RF) power amplifier (PA) having a first final stage and adapted to;

receive and amplify a first RF input signal to provide a first RF output signal; and

receive a first final bias signal to bias the first final stage;

PA bias circuitry adapted to receive a bias power supply signal and provide the first final bias signal based on the bias power supply signal; and

a direct current (DC)-DC converter adapted to receive a DC power supply signal from a DC power supply and provide the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal.

24. The circuitry of claim 1 further comprising:

a direct current (DC)-DC converter comprising;

a power amplifier (PA) envelope power supply comprising a charge pump buck converter coupled to radio frequency (RF) PA circuitry;

the first programmable frequency oscillator; and

a PA bias power supply comprising a charge pump coupled to the RF PA circuitry; and

the RF PA circuitry.

25. The circuitry of claim 24 wherein the first ramp comparator output signal is a first clock signal, such that the first programmable frequency oscillator provides the first clock signal to the PA envelope power supply.

26. The circuitry of claim 24 wherein the ramping signal is a first clock signal, such that the first programmable frequency oscillator provides the first clock signal to the PA envelope power supply.

27. The circuitry of claim 1 further comprising:

multi-mode multi-band radio frequency (RF) power amplification circuitry having at least a first RF input and a plurality of RF outputs, such that;

configuration of the multi-mode multi-band RF power amplification circuitry associates one of the at least the first RF input with one of the plurality of RF outputs; and

the configuration is associated with at least a first look-up table (LUT);

power amplifier (PA) control circuitry coupled between the multi-mode multi-band RF power amplification circuitry and a PA-digital communications interface (DCI), such that the PA control circuitry has at least the first LUT, which is associated with at least a first defined parameter set; and

the PA-DCI, which is coupled to a digital communications bus.

28. A method for generating a programmable frequency oscillator comprising:

providing a first ramp comparator having a first propagation delay;

providing programmable signal generation circuitry;

receiving a ramping signal having a first frequency based on a desired first frequency;

providing a first ramp comparator output signal based on the ramping signal;

providing the ramping signal based on the desired first frequency and the first ramp comparator output signal; and

compensating for the first propagation delay based on the desired first frequency.