Clock driven dynamic datapath chaining

• US 8,516,025 B2
• Filed: 04/16/2008
• Issued: 08/20/2013
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sullam, Bert, Synder, Warren
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US12/104,391
• Publication Number:
  US 20080288755A1
• Time in Patent Office: 1,952 Days
• Field of Search: None
• US Class Current: 708/233
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables

Abstract

A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.

Claims

1. An apparatus, comprising:

a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data; and

a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations, where the datapaths receive the configuration data based on a clock cycle, and the datapaths are dynamically chained to collaborate on the arithmetic operations according to configuration data and the clock cycle.

2. The apparatus according to claim 1, where a first datapath receives a chained carry-in value from a second datapath for utilization in the arithmetic operations.

3. The apparatus according to claim 2, where the first datapath includes a multiplexor to at least receive a chained carry-in value from the second datapath, the multiplexor to provide the first datapath the chained carry-in value according to the configuration data from the configuration memory.

4. The apparatus according to claim 3, where the multiplexor is operable to receive the chained carry-in value and one or more of a default carry-in value, a registered carry-in value, a carry-in value received from an interconnect routing.

5. The apparatus according to claim 2, where the chained carry-in value received by the first datapath is a carry-out value of the second datapath.

6. The apparatus according to claim 1, where the datapaths are operable to perform time-division multiplexed arithmetic operations according to the configuration data, where the datapaths are dynamically chained to collaborate on the arithmetic operations during a first clock cycle and unchained to perform independent arithmetic operations during a second clock cycle.

7. A method comprising:

receiving a chained carry-in value from a datapath and receiving configuration data from a configuration memory based on a clock cycle;

selecting the chained carry-in value according to the configuration data from the configuration memory; and

dynamically chaining to the datapath according to the configuration data and the clock cycle to collaborate with the datapath in the performance of arithmetic operations by utilizing the chained carry-in selected according to the configuration data when performing arithmetic operations.

8. The method according to claim 7, includes multiplexing multiple input values according to the configuration data, where at least one of the input values is the chained carry-in value received from the datapath.

9. The method according to claim 8, where the input values include one or more of a default carry-in value, a registered carry-in value, a carry-in value received from an interconnect routing.

10. The method according to claim 7, where the chained carry-in value is a carry-out value of the datapath.

11. The method according to claim 7, includes:

dynamically chaining to the datapath for collaborate on the arithmetic operations during a first clock cycle; and

dynamically unchaining to perform independent arithmetic operations during a second clock cycle.

12. A device comprising:

a structural arithmetic circuit to perform various arithmetic operations based, at least in part, on configuration data; and

a selection circuit to receive a chained carry-in value from a datapath, and select the chained carry-in value according to the configuration data, where the structural arithmetic circuit to perform arithmetic operations by utilizing the chained carry-in selected, where the selection circuit is operable to receive the configuration data based on a clock cycle, and the structural arithmetic circuit to dynamically chain to the datapath for collaboration on the arithmetic operations according to configuration data and the clock cycle.

13. The device according to claim 12, where the selection circuit is operable to multiplex multiple input values according to the configuration data, where at least one of the input values is the chained carry-in value received from the datapath.

14. The device according to claim 13, where the input values include one or more of a default carry-in value, a registered carry-in value, a carry-in value received from an interconnect routing.

15. The device according to claim 12, where the chained carry-in value is a carry-out value of the datapath.

16. The device according to claim 12, where the structural arithmetic circuit is operable to dynamically chain to the datapath for collaborate on the arithmetic operations during a first clock cycle, and then dynamically unchaining to perform independent arithmetic operations during a second clock cycle.

17. The device according to claim 12, where the structural arithmetic circuit is operable to dynamically chain and unchain to the datapath on alternate clock cycles to time-division multiplex performance of arithmetic operations.