Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface
First Claim
1. A serial buffer comprising:
- a plurality of queues configured to store data packets received from a host;
a direct memory access (DMA) engine coupled to receive data packets read from the queues;
a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine, and wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within a system memory, and wherein each of the DMA register sets include a wrap/stop register configured to store a wrap_stop identifier that indicates whether or not the buffer is accessed in a wrap-around manner; and
circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to the system memory using the corresponding DMA channel.
3 Assignments
0 Petitions
Accused Products
Abstract
A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.
36 Citations
14 Claims
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1. A serial buffer comprising:
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a plurality of queues configured to store data packets received from a host; a direct memory access (DMA) engine coupled to receive data packets read from the queues; a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine, and wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within a system memory, and wherein each of the DMA register sets include a wrap/stop register configured to store a wrap_stop identifier that indicates whether or not the buffer is accessed in a wrap-around manner; and circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to the system memory using the corresponding DMA channel. - View Dependent Claims (2, 3, 4, 5, 7, 8, 9, 10, 11, 12)
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6. A serial buffer comprising:
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a plurality of queues configured to store data packets received from a host; a direct memory access (DMA) engine coupled to receive data packets read from the queues; and a plurality of DMA register sets, wherein each of the DMA register sets is configured to store parameters that define a corresponding DMA channel of the DMA engine, and wherein each of the DMA register sets include a start address register configured to store a start address and a stop address register configured to store a stop address, wherein the start address and the stop address define a unique buffer within a system memory, and wherein each of the DMA register sets include a wrap/stop doorbell register configured to store a wrap stop doorbell enable signal that indicates whether or not the serial buffer transmits a doorbell to the host when the DMA engine implements a transfer to an associated stop address; and circuitry for selecting one of the DMA register sets to configure the DMA engine, thereby enabling the DMA engine to transfer the received data packets to the system memory using the corresponding DMA channel.
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13. A serial buffer comprising:
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a queue configured to store data packets received from a host, wherein the queue has a queue channel select value and a queue/packet select value; a direct memory access (DMA) engine coupled to receive data packets read from the queue; a plurality of DMA register sets, each storing parameters that define a corresponding DMA channel of the DMA engine; and means for selecting one of the DMA register sets to configure the DMA engine, wherein the means for selecting selects one of the DMA register sets in response to the queue channel select value when the queue/packet select value has a first value, and wherein the means for selecting selects one of the DMA register sets in response to a packet channel select value included in each of the data packets read from the queue when the queue/packet select value has a second value.
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14. A serial buffer comprising:
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a plurality of queues configured to store data packets received from a host, each of the queues having a corresponding queue channel select value and a corresponding queue/packet select value; a direct memory access (DMA) engine coupled to receive data packets read from the queues; a plurality of DMA register sets, each storing parameters that define a corresponding DMA channel of the DMA engine; and means for selecting one of the DMA register sets to configure the DMA engine, wherein the means for selecting selects one of the DMA register sets in response to the queue channel select value corresponding with a queue being read when the queue/packet select value has a first value, and wherein the means for selecting selects one of the DMA register sets in response to a packet channel select value included in a data packet retrieved from the queue being read when the queue/packet select value has a second value.
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Specification