Programmable memory system

• US 8,516,178 B2
• Filed: 06/19/2012
• Issued: 08/20/2013
• Est. Priority Date: 03/08/2000
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okamoto, Kosei, Sakamoto, Hiroyuki, Fujimoto, Akihisa, Suga, Masao
• Primary Examiner(s): Cleary, Thomas J
• Application Number:
  US13/527,140
• Publication Number:
  US 20120260001A1
• Time in Patent Office: 427 Days
• Field of Search: 710/11, 710/14, 710/16, 710 62- 63, 710/105, 710301-302
• US Class Current: 710/301
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H05K 7/10 Plug-in assemblages of components , e.g. IC sockets

Abstract

In one embodiment, a system having a non-volatile programmable memory and a controller is provided. The system has data pins that are configured to be accessed in one of a first mode and a second mode such that, in the first mode, the system receives information using one of the data pins and, in the second mode, the system receives information using four of the data pins. The system also has a command pin that is configured to receive a first command, a second command, and a third command, the first command requesting a current operation mode of the data pins, the second command requesting operation voltage information of the system, and the third command setting the system into one of the first and second modes. Additionally, the system has a power signal pin configured to receive power for the system.

Claims

1. A system having a non-volatile programmable memory and a controller, said system comprising:

data pins that are configured to be accessed in one of a first mode and a second mode such that, in the first mode, the system receives information using one of the data pins and, in the second mode, the system receives information using four of the data pins;

a command pin that is configured to receive a first command, a second command, and a third command, said first command requesting a current operation mode of said data pins, said second command requesting operation voltage information of said system, and said third command setting said system into one of said first and second modes; and

a power signal pin configured to receive power for said system.

2. The system according to claim 1, wherein the controller is configured to receive power voltage information concerning a power voltage.

3. The system according to claim 2, wherein the controller is configured to transmit a response if the system can operate with the power voltage.

4. The system according to claim 2, wherein the controller is configured to receive an initial voltage via the power signal pin before receiving the power voltage information.

5. The system according to claim 4, wherein the initial voltage differs from the power voltage.

6. The system according to claim 1, wherein the controller is configured to receive a fourth command for reading an address, assigned to the system via the command pin, and

wherein the controller is configured to transmit the address via the command pin in response to the fourth command.

7. The system according to claim 6, wherein the controller is configured to receive a fifth command for selecting the system, the fifth command including an address indicating a system to be selected;

and

wherein the controller is configured to shift the system to a selected state if the address included in the fifth command is identical to the address assigned to the system.

8. The system according to claim 1, wherein the controller is configured to receive a fourth command for reading identification data, unique to the system via the command pin;

and

wherein the controller is configured to transmit the identification data via the command pin in response to the fourth command.

9. The system according to claim 8, wherein the controller is configured to shift the system from a ready state to an identification state after transmitting the identification.