Circuitry for active cable

• US 8,516,238 B2
• Filed: 06/30/2011
• Issued: 08/20/2013
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Cornelius, William P., Ferry, William O., Orr, James E.
• Primary Examiner(s): WANG, ALBERT C
• Application Number:
  US13/173,739
• Publication Number:
  US 20120000705A1
• Time in Patent Office: 782 Days
• Field of Search: 385/89, 398/155, 398/167, 713/100, 713/500, 714/716
• US Class Current: 713/100
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2370/04 Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 2370/12 Use of DVI or HDMI protocol in interfaces along the display data pipeline
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H01R 29/00 Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors

Abstract

Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy standard in one mode and a newer standard in another mode.

Claims

1. An active cable comprising:

a cable;

a first plug connected to a first end of the cable and comprising;

a first clock and data recovery circuit to retime signals received at an input of the first plug;

a second clock and data recovery circuit to retime signals received from the cable; and

a first microcontroller to configure the first clock and data recovery circuit and the second clock and data recovery circuit; and

a second plug connected to a second end of the cable and comprising;

a third clock and data recovery circuit to retime signals received at an input of the second plug;

a fourth clock and data recovery circuit to retime signals received from the cable; and

a second microcontroller to configure the third clock and data recovery circuit and the fourth clock and data recovery circuit,

wherein the first microcontroller can configure an output of the first clock and data recovery circuit to couple to an input of the second clock and data recovery circuit.

2. The active cable of claim 1 wherein the cable connects an output of the first clock and data recovery circuit to an input of the fourth clock and data recovery circuit and an output of the third clock and data recovery circuit to an input of the second clock and data recovery circuit.

3. The active cable of claim 1 wherein the first microcontroller and the second microcontroller are programmable using pins on the first plug and the second plug.

4. The active cable of claim 1 wherein the first clock and data recovery circuit includes an equalizer circuit.

5. The active cable of claim 1 wherein the first clock and data recovery circuit comprises a de-emphasis circuit.

6. An active cable comprising:

a cable;

a first plug connected to a first end of the cable and comprising;

a first clock and data recovery circuit to retime signals received at an input of the first plug;

a second clock and data recovery circuit to retime signals received from the cable; and

a first microcontroller to configure the first clock and data recovery circuit and the second clock and data recovery circuit; and

a second plug connected to a second end of the cable and comprising;

a third clock and data recovery circuit to retime signals received at an input of the second plug;

a fourth clock and data recovery circuit to retime signals received from the cable; and

a second microcontroller to configure the third clock and data recovery circuit and the fourth clock and data recovery circuit,

wherein the first microcontroller can configure an output of the second clock and data recovery circuit to couple to an input of the first clock and data recovery circuit.

7. The active cable of claim 6 wherein the cable connects an output of the first clock and data recovery circuit to an input of the fourth clock and data recovery circuit and an output of the third clock and data recovery circuit to an input of the second clock and data recovery circuit.

8. The active cable of claim 6 wherein the first microcontroller and the second microcontroller are programmable using pins on the first plug and the second plug.

9. The active cable of claim 6 wherein the first clock and data recovery circuit includes an equalizer circuit.

10. The active cable of claim 6 wherein the first clock and data recovery circuit comprises a de-emphasis circuit.