Multi-votage synchronous systems

• US 8,516,300 B2
• Filed: 01/13/2009
• Issued: 08/20/2013
• Est. Priority Date: 08/29/2005
• Status: Expired due to Fees

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Mangione-Smith, William Henry
• Primary Examiner(s): Leibovich, Yair
• Application Number:
  US12/321,027
• Publication Number:
  US 20090150713A1
• Time in Patent Office: 1,680 Days
• Field of Search: 714/10, 714/2, 714/25, 714/37, 714/38.1, 714/14, 713/300
• US Class Current: 714/14
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments include a system, a device, and a method. A computing system includes a synchronous circuit. The synchronous circuit includes a first subcircuit powered by a first power plane having a first power plane voltage and a second subcircuit powered by a second power plane having a second power plane voltage. The system also includes an error detector operable to detect an incidence of a computational error occurring in the first subcircuit. The system further includes a controller operable to change the first power plane voltage based upon the detected incidence of a computational error. The system may include a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

Claims

1. A computing system comprising:

an integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage;

an error detector operable to execute a process to detect an incidence of a computational error occurring in the first subcircuit; and

a controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage.

2. The computing system of claim 1, wherein the integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage comprises:

a synchronous processor including (i) a first processor core powered by a first power plane having a first power plane voltage and (ii) a second processor core powered by a second power plane having a second power plane voltage.

3. The computing system of claim 1, wherein the integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage comprises:

a synchronous uniprocessor including (i) a first subsystem powered by a first power plane having a first power plane voltage and (ii) a second subsystem powered by a second power plane having a second power plane voltage.

4. The computing system of claim 1, wherein the integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage comprises:

a synchronous uniprocessor including (i) a first arithmetic logic unit powered by a first power plane having a first power plane voltage and (ii) a second arithmetic logic unit powered by a second power plane having a second power plane voltage.

5. The computing system of claim 1, wherein the integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage comprises:

a synchronous uniprocessor including (i) an arithmetic logic unit powered by a first power plane having a first power plane voltage and (ii) an on-chip cache powered by a second power plane having a second power plane voltage.

6. The computing system of claim 1, wherein the error detector operable to execute a process to detect an incidence of a computational error occurring in the first subcircuit comprises:

a hardware-implemented error detector operable to detect an incidence of a computational error occurring in the first subcircuit.

7. The computing system of claim 1, wherein the error detector operable to execute a process to detect an incidence of a computational error occurring in the first subcircuit comprises:

one error detector (i) coupled with both the first subcircuit and the second subcircuit and (ii) operable to detect an incidence of a computational error occurring in the first subcircuit.

8. The computing system of claim 7, wherein the one error detector (i) coupled with both the first subcircuit and the second subcircuit and (ii) operable to detect an incidence of a computational error occurring in the first subcircuit comprises:

one error detector (i) coupled with both the first subcircuit and the second subcircuit and (ii) operable to detect an incidence of a computational error occurring in the first subcircuit or the second subcircuit.

9. The computing system of claim 1, wherein the error detector operable to execute a process to detect an incidence of a computational error occurring in the first subcircuit comprises:

a first error detector coupled with the first subcircuit and a second error detector coupled with the second subcircuit, the first error detector and the second error detector respectively being operable to detect an incidence of a computational error occurring in the first subcircuit and the second sub circuit.

10. The computing system of claim 1, wherein the error detector operable to execute a process to detect an incidence of a computational error occurring in the first subcircuit comprises:

an error detector coupled with the controller and operable to detect an incidence of a computational error occurring in the first subcircuit.

11. The computing system of claim 1, wherein the integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage comprises:

an integrated circuit chip including at least one synchronous circuit including (i) a first arithmetic logic unit powered by a first power plane having a first power plane voltage and (ii) a second arithmetic logic unit powered by a second power plane having a second power plane voltage.

12. The computing system of claim 1, wherein the detected incidence of a computational error corresponds to at least one of a setup/hold violation, a noise spike, a charged particle, a single event upset failure, an unreliable processor hardware, an incorrectly executed instruction, an oxide breakdown, an electromigration induced error, a processor clock speed, a processor voltage, a soft error, an on-chip cache error, or an induced error.

13. The computing system of claim 1, wherein the error detector operable to execute a process to detect an incidence of a computational error occurring in the first subcircuit comprises:

an error detector operable to detect at least one of a single incidence, an incidence frequency, an incidence occurrence rate, an incidence tempo, an incidence pattern, or an incidence prevalence of a computational error.

14. The computing system of claim 1, wherein the controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage comprises:

a controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without substantially increasing the second power plane voltage.

15. The computing system of claim 1, wherein the controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage comprises:

a controller operable to decrease the first power plane voltage based upon a detected incidence of a computational error occurring in the first subcircuit without a logically corresponding decrease in the second power plane voltage.

16. The computing system of claim 1, wherein the controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage comprises:

a controller (i) implemented in at least one of hardware, software, firmware, or a microengine and (ii) operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage.

17. The computing system of claim 1, wherein the controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage comprises:

a controller implemented in software associated with at least one of an operating system or a program executable by the integrated circuit chip and operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage.

18. The computing system of claim 1, wherein the integrated circuit chip including at least one synchronous circuit including (i) a first subcircuit powered by a first power plane having a first power plane voltage and (ii) a second subcircuit powered by a second power plane having a second power plane voltage comprises:

an integrated circuit chip including at least one synchronous circuit including (i) an arithmetic logic unit powered by a first power plane having a first power plane voltage and (ii) a cache powered by a second power plane having a second power plane voltage.

19. The computing system of claim 1, wherein the controller operable to increase the first power plane voltage based upon the detected incidence of a computational error without a logically corresponding increase in the second power plane voltage comprises:

a controller operable to decrease the first power plane voltage based upon a detected incidence of a computational error occurring in the first subcircuit.

20. The computing system of claim 1, wherein the at least one synchronous circuit, the error detector, and the controller are formed on the integrated circuit chip.

21. The computing system of claim 1, further comprising:

a recovery module operable to cause a correction of the computational error.

22. The computing system of claim 1, further comprising:

a power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

23. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller comprises:

a power supply operable to provide in response to the controller a selected voltage to the first power plane and another selected voltage to the second power plane.

24. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller comprises:

a power supply, which is on the integrated circuit chip, operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

25. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller comprises:

a power supply, which is off the integrated circuit chip and electrically coupled with the integrated circuit chip, operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

26. The computing system of claim 22, wherein the power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller comprises:

at least one of a DC/DC regulated, a controllable, or a programmable power supply operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

27. The computing system of claim 1, further comprising:

a power supply configured to electrically engage a portable power source and operable to provide a selected one of at least two voltages to the first power plane in response to the controller.

28. A method implemented in a computing system, the method comprising:

detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage; and

increasing the first power plane voltage based upon the detected computational error without a logically corresponding increase in the second power plane voltage.

29. The method of claim 28, wherein the detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage, comprises:

detecting a computational error occurring in a first processor core of a synchronous processor of an integrated circuit chip, the synchronous processor including (i) the first processor core powered by a first power plane at a first power plane voltage and (ii) a second processor core powered by a second power plane at a second power plane voltage.

30. The method of claim 28, wherein the detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage, comprises:

detecting a computational error occurring in a first subcircuit of a synchronous uniprocessor of an integrated circuit chip, the synchronous uniprocessor including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage.

31. The method of claim 28, wherein the increasing the first power plane voltage based upon the detected computational error without a logically corresponding increase in the second power plane voltage comprises:

increasing the first power plane voltage based upon the detected computational error while maintaining the second power plane voltage at least substantially constant.

32. The method of claim 28, wherein the increasing the first power plane voltage based upon the detected computational error without a logically corresponding increase in the second power plane voltage comprises:

increasing the first power plane voltage based upon the detected computational error without a logically corresponding change in the second power plane voltage.

33. The method of claim 28, further comprising:

operating the first subcircuit at a first power plane voltage.

34. The method of claim 33, wherein the operating the first subcircuit at a first power plane voltage comprises:

operating the first subcircuit at an initial first power plane voltage.

35. The method of claim 28, further comprising:

decreasing the first power plane voltage.

36. The method of claim 28, wherein the detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage, comprises:

detecting a computational error occurring in a first arithmetic logic unit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first arithmetic logic unit powered by a first power plane at a first power plane voltage and (ii) a second arithmetic logic unit powered by a second power plane at a second power plane voltage.

37. The method of claim 28, wherein the detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage, comprises:

detecting a computational error occurring in an arithmetic logic unit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the arithmetic logic unit powered by a first power plane at a first power plane voltage and (ii) a cache powered by a second power plane at a second power plane voltage.

38. A computing device comprising:

means for detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage, wherein the means for detecting is capable of detecting computational errors that correspond to a setup/hold violation, a noise spike, a charged particle, a single event upset failure, an unreliable processor hardware, an incorrectly executed instruction, an oxide breakdown, and an electromigration induced error; and

means for increasing the first power plane voltage based upon the detected computational error.

39. The computing device of claim 38, further comprising:

means for operating the first subcircuit at an initial first power plane voltage.

40. The computing device of claim 38, further comprising:

means for decreasing the first power plane voltage.

41. A computing device comprising:

means for detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage; and

means for increasing the first power plane voltage based upon the detected computational error without a logically corresponding increase in the second power plane voltage.

42. The computing device of claim 41, wherein the means for detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage, comprises:

means for detecting a computational error occurring in a first arithmetic logic unit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first arithmetic logic unit powered by a first power plane at a first power plane voltage and (ii) a second arithmetic logic unit powered by a second power plane at a second power plane voltage.

43. The computing device of claim 41, wherein the means for detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the first subcircuit powered by a first power plane at a first power plane voltage and (ii) a second subcircuit powered by a second power plane at a second power plane voltage, comprises:

means for detecting a computational error occurring in an arithmetic logic unit of a synchronous circuit of an integrated circuit chip, the synchronous circuit including (i) the arithmetic logic unit powered by a first power plane at a first power plane voltage and (ii) a cache powered by a second power plane at a second power plane voltage.

44. A method implemented in a computing system, the method comprising:

detecting, at least partially by executing a process, a computational error occurring in a first subcircuit of a synchronous circuit that includes the first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage, wherein the detecting is capable of detecting computational errors that correspond to a setup/hold violation, a noise spike, a charged particle, a single event upset failure, an unreliable processor hardware, an incorrectly executed instruction, an oxide breakdown, and an electromigration induced error; and

increasing the first power plane voltage based upon the detected computational error.

45. A computing system comprising:

a synchronous circuit including a first subcircuit powered by a first power plane at a first power plane voltage and a second subcircuit powered by a second power plane at a second power plane voltage;

an error detector operable to execute a process to detect a computational error occurring in the first subcircuit of the synchronous circuit, wherein the error detector is capable of detecting computational errors that correspond to a setup/hold violation, a noise spike, a charged particle, a single event upset failure, an unreliable processor hardware, an incorrectly executed instruction, an oxide breakdown, and an electromigration induced error; and

a controller operable to increase the first power plane voltage based upon the detected computational error.