Method and apparatus for automatically fixing double patterning loop violations
First Claim
1. A non-transitory machine readable medium storing a program for resolving a design rule violation in a circuit design layout including a plurality of shapes, the program comprising sets of instructions for:
- identifying a double patterning loop formed by a set of shapes in the design layout, the double patterning loop representing a design rule violation;
identifying critical portions of the set of shapes, wherein a critical portion is a portion of a shape that is within a threshold distance from another shape;
assigning the critical portions of the set of shapes to a plurality of masks in a manner that reduces a number of cut graphs to be inserted in each shape of the set of shapes, the cut graphs for partitioning the shape into a plurality of segments so that at least two different segments of the shape are assignable to two different masks;
inserting cut graphs into the design layout based on the assignment of the critical portions of the set of shapes to the plurality of masks;
partitioning the shapes based on the inserted cut graphs; and
assigning, for each partitioned shape, at least two different partitions to two different masks, in order to resolve the design rule violation due to the double patterning loop.
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Accused Products
Abstract
A method for automatically decomposing a shape of an IC design layout into two or more shapes in order to resolve a double patterning loop violation involving the shape. The method decomposes the shape by introducing one or more splicing graphs on the shape. These splicing graphs serve as cuts to be made on the shape. By decomposing the shape into several shapes and assigning the shapes to alternating masks for the same layer, the method breaks the double patterning loop. That is, no pair of the shape and other shapes that form the loop will be assigned to the same color for a mask after the shape is decomposed. In some embodiments, the method introduces splicing points to more than one shape of the loop-forming shapes when necessary. Some embodiments minimize the number of splicing points introduced to the shape(s).
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Citations
29 Claims
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1. A non-transitory machine readable medium storing a program for resolving a design rule violation in a circuit design layout including a plurality of shapes, the program comprising sets of instructions for:
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identifying a double patterning loop formed by a set of shapes in the design layout, the double patterning loop representing a design rule violation; identifying critical portions of the set of shapes, wherein a critical portion is a portion of a shape that is within a threshold distance from another shape; assigning the critical portions of the set of shapes to a plurality of masks in a manner that reduces a number of cut graphs to be inserted in each shape of the set of shapes, the cut graphs for partitioning the shape into a plurality of segments so that at least two different segments of the shape are assignable to two different masks; inserting cut graphs into the design layout based on the assignment of the critical portions of the set of shapes to the plurality of masks; partitioning the shapes based on the inserted cut graphs; and assigning, for each partitioned shape, at least two different partitions to two different masks, in order to resolve the design rule violation due to the double patterning loop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer-implemented method for resolving a design rule violation in a circuit design layout including a plurality of shapes, the method comprising:
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identifying, at a computer, that an odd number of shapes form a loop in which each pair of neighboring-shapes has the pair'"'"'s two shapes closer than a threshold distance; identifying critical portions in the shapes that form the loop, wherein a critical portion is a portion of a shape that is within the threshold distance from another shape; assigning the critical portions of the shapes that form the loop to a plurality of masks according to criteria that reduce a number of cut graphs to be inserted in each shape of the shapes that form the loop, the cut graphs for partitioning the shape into a plurality of segments so that at least two different segments of the shape are assignable to two different masks; inserting cut graphs into the design layout based on the assignment of the critical portions of the shapes that form the loop to the plurality of masks; and breaking the loop by dividing at least one shape of the loop into two or more segments based on the inserted cut graphs to assign the segments to two different masks. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A system comprising:
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a processor for executing sets of instructions; and a memory for storing a computer program for correcting a design rule violation in a circuit design layout including a plurality of shapes, the program comprising sets of instructions for; identifying a double patterning loop formed by a set of shapes in the design layout, the double patterning loop representing a design rule violation; identifying critical portions of the set of shapes, wherein a critical portion is a portion of a shape that is within a threshold distance from another shape; assigning the critical portions of the set of shapes to a plurality of masks in a manner that reduces a number of cut graphs to be inserted in each shape of the set of shapes, the cut graphs for partitioning the shape into a plurality of segments so that at least two different segments of the shape are assignable to two different masks; inserting cut graphs into the design based on the assignment of the critical portions of the set of shapes to the plurality of masks; partitioning the shapes based on the inserted cut graphs; and assigning, for each partitioned shape, at least two different partitions to two different masks, in order to resolve the design rule violation due to the double patterning loop. - View Dependent Claims (27, 28, 29)
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Specification