Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model

• US 8,516,420 B1
• Filed: 08/31/2007
• Issued: 08/20/2013
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Kariat, Vinod, Keller, Igor, Phillips, Joel R., Tam, King Ho
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US11/849,254
• Time in Patent Office: 2,181 Days
• Field of Search: 716/108, 716/113, 716/115, 703/14
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

In one embodiment of the invention, a multi-CCC current source model is disclosed to perform statistical timing analysis of an integrated circuit design. The multi-CCC current source model includes a voltage waveform transfer function, a voltage dependent current source, and an output capacitor. The voltage waveform transfer function receives an input voltage waveform and transforms it into an intermediate voltage waveform. The voltage dependent current source generates an output current in response to the intermediate voltage waveform. The output capacitor is coupled in parallel to the voltage dependent current source to generate an output voltage waveform for computation of a timing delay.

Claims

1. A method of characterizing a standard cell for a cell library, the method comprising:

characterizing a standard cell for a voltage transform function of a transform stage of a multi-channel-connected component (multi-CCC) current source model with a plurality of input signal waveforms having different slew rates, the voltage transform function to transform an input voltage waveform with a given slew rate into an intermediate voltage waveform;

characterizing parasitic capacitances of the standard cell; and

characterizing the standard cell for an output current for a driving stage of the multi-CCC current source model;

wherein at least one of the characterizing processes is performed with a processor.

2. The method of claim 1, wherein

the characterizing of the output current includes

simulating circuits including transistors in the standard cell using a transistor level circuit simulator,

holding the output of the standard cell to a constant output voltage,

switching one input of the standard cell using an input signal waveform having a reference slew rate, and

measuring the output current from the output of the standard cell in response to the input signal waveform with the reference slew rate.

3. The method of claim 2, further comprising:

tabulating the results of the measuring of the output current.

4. The method of claim 2, further comprising:

repeating the characterizing of the output current for an incrementally different constant output voltage over a range of power supply voltages from zero volts to a positive power supply voltage.

5. The method of claim 4, further comprising:

tabulating the results of each measurement of the output current for each constant output voltage.

6. The method of claim 5, wherein

the characterizing of the parasitic capacitances of the standard cell includes

further simulating circuits including transistors in the standard cell using a transistor level circuit simulator,

holding inputs of the standard cell to a constant input voltage,

ramping a voltage source coupled to the output of the standard cell with a predetermined slew rate over a range from zero volts to a positive power supply voltage,

measuring a current through the voltage source,

looking up an expected output current for the standard cell from the tabulated results of the output current, and

calculating the output impedance of the standard cell in response to the measured current, the expected output current, the predetermined slew rate, and the positive power supply voltage.

7. The method of claim 6, wherein

the calculating includes

subtracting the expected output current from the measured current to generate a difference,

multiplying the difference and the predetermined slew rate together to generate a product, and

dividing the product with the positive power supply voltage.

8. The method of claim 1, wherein

the characterizing of the parasitic capacitances of the standard cell includes

simulating circuits including transistors in the standard cell using a transistor level circuit simulator,

holding inputs of the standard cell to a constant input voltage,

ramping a voltage source coupled to the output of the standard cell with a predetermined slew rate over a range from zero volts to a positive power supply voltage,

measuring a current through the voltage source,

looking up an expected output current for the standard cell from a table of output current values, and

calculating the output impedance of the standard cell in response to the measured current, the expected output current, the predetermined slew rate, and the positive power supply voltage.

9. The method of claim 8, wherein

the calculating includes

subtracting the expected output current from the measured current to generate a difference,

multiplying the difference and the predetermined slew rate together to generate a product, and

dividing the product with the positive power supply voltage.

10. The method of claim 1, wherein

the characterizing of the voltage transform function of the standard cell includes

simulating circuits including transistors in the standard cell using a transistor level circuit simulator,

holding the output of the standard cell to a constant output voltage,

switching one input of the standard cell using an input signal waveform having a predetermined slew rate, and

measuring the output current from the output of the standard cell in response to the input signal waveform having the predetermined slew rate.

11. The method of claim 10, wherein

the input signal waveform is a ramp input signal.

12. The method of claim 11, wherein

the constant output voltage is one-third of the positive power supply voltage, if the output of the standard cell would ordinarily rise in response to the ramp input signal.

13. The method of claim 11, wherein

the constant output voltage is two-thirds of the positive power supply voltage, if the output of the standard cell would ordinarily fall in response to the ramp input signal.

14. The method of claim 10, wherein

the predetermined slew rate differs from a reference slew rate and the method further includes

tabulating the results of the measuring of the output current,

comparing the input signal waveform with the output current waveform to determine extra delay time, a base delay parameter value T_σ

, and a slope shift parameter value τ

_σ

,

normalizing the output current waveform using the base delay and the slope shift parameter values,

normalizing a reference output current waveform, and

aligning the normalized reference output current waveform and the normalized output current waveform together and recording equi-current time points.

15. The method of claim 14, further comprising:

repeating the characterizing of the output current for the driving stage of the standard cell with another predetermined slew rate differing from the reference slew rate.

16. The method of claim 1, further comprising:

characterizing the standard cell for a miller capacitance coupled between the transform stage and the driving stage of the multi-CCC current source model.

17. The method of claim 16, wherein

the characterizing of the standard cell for the miller capacitance includes

simulating circuits including transistors in the standard cell using a transistor level circuit simulator,

holding the output of the standard cell to a constant output voltage with a voltage source coupled to the output of the standard cell,

switching one input of the standard cell using a ramp input signal waveform with a fast slew rate,

measuring the output current into the voltage source to determine a miller current and a switching delay time,

estimating a change in voltage over a time period in the miller capacitance, and

calculating the miller capacitance in response to the miller current and the change in voltage over the time period in the miller capacitance.

18. The method of claim 17, wherein

the constant output voltage is the positive power supply voltage, if the output of the standard cell would ordinarily fall in response to the ramp input signal.

19. The method of claim 17, wherein

the constant output voltage is zero volts, if the output of the standard cell would ordinarily rise in response to the ramp input signal.

20. The method of claim 17, wherein

the change in voltage over the time period in the miller capacitance is estimated by dividing the positive power supply voltage with the switching delay time.

21. The method of claim 20, wherein

the miller capacitance is calculated by dividing the miller current with the change in voltage over the time period in the miller capacitance.

22. The method of claim 1, wherein

the output current for the driving stage of the multi-CCC current source model is responsive to the intermediate voltage.

23. The method of claim 1, wherein

the standard cell is a multi-CCC standard cell.

24. A system for characterizing a standard cell of a cell library, the system comprising:

one or more processors to execute instructions; and

a storage device coupled to the one or more processors, the storage device to store instructions including

instructions to characterize a standard cell for a voltage transform function of a transform stage of a multi-channel-connected component (multi-CCC) current source model with a plurality of input signal waveforms having different slew rates, the voltage transform function to transform an input voltage waveform with a given slew rate into an intermediate voltage waveform;

instructions to characterize parasitic capacitances of the standard cell; and

instructions to characterize the standard cell for an output current for a driving stage of the multi-CCC current source model.

25. The system of claim 24, wherein

the instructions to characterize the standard cell for the output current includes

instructions to simulate circuits including transistors in the standard cell using a transistor level circuit simulator,

instructions to hold the output of the standard cell to a constant output voltage,

instructions to switch one input of the standard cell using an input signal waveform having a reference slew rate, and

instructions to measure the output current from the output of the standard cell in response to the input signal waveform with the reference slew rate.

26. The system of claim 24, wherein

the instructions to characterize the parasitic capacitances of the standard cell includes

instructions to simulate circuits including transistors in the standard cell using a transistor level circuit simulator,

instructions to hold inputs of the standard cell to a constant input voltage,

instructions to ramp a voltage source coupled to the output of the standard cell with a predetermined slew rate over a range from zero volts to a positive power supply voltage,

instructions to measure a current through the voltage source,

instructions to look up an expected output current for the standard cell from a table of output current values, and

instructions to calculate the output impedance of the standard cell in response to the measured current, the expected output current, the predetermined slew rate, and the positive power supply voltage.

27. The system of claim 24, wherein

the instructions to characterize the voltage transform function of the standard cell includes

instructions to simulate circuits including transistors in the standard cell using a transistor level circuit simulator,

instructions to hold the output of the standard cell to a constant output voltage,

instructions to switch one input of the standard cell using an input signal waveform having a predetermined slew rate, and

instructions to measure the output current from the output of the standard cell in response to the input signal waveform having the predetermined slew rate.

28. The system of claim 27, wherein

the predetermined slew rate differs from a reference slew rate, and

the instructions stored in the storage device further includes

instructions to tabulate the results of the measuring of the output current,

instructions to compare the input signal waveform with the output current waveform to determine extra delay time, a base delay parameter value T_σ

, and a slope shift parameter value τ

_σ

,

instructions to normalize the output current waveform using the base delay and the slope shift parameter values,

instructions to normalize a reference output current waveform, and

instructions to align the normalized reference output current waveform and the normalized output current waveform together and recording equi-current time points.

29. The system of claim 24, the instructions stored in the storage device further includes:

instructions to characterize the standard cell for a miller capacitance coupled between the transform stage and the driving stage of the multi-CCC current source model.

30. The system of claim 29, wherein

the instructions to characterize the standard cell for the miller capacitance includes

instructions to simulate circuits including transistors in the standard cell using a transistor level circuit simulator,

instructions to hold the output of the standard cell to a constant output voltage with a voltage source coupled to the output of the standard cell,

instructions to switch one input of the standard cell using a ramp input signal waveform with a fast slew rate,

instructions to measure the output current into the voltage source to determine a miller current and a switching delay time,

instructions to estimate a change in voltage over a time period in the miller capacitance, and

instructions to calculate the miller capacitance in response to the miller current and the change in voltage over the time period in the miller capacitance.

31. A computer readable product to characterize a standard cell of a cell library, the computer readable product comprising:

a computer readable storage device storing instructions including

instructions to characterize a standard cell for a voltage transform function of a transform stage of a multi-channel-connected component (multi-CCC) current source model with a plurality of input signal waveforms having different slew rates, the voltage transform function to transform an input voltage waveform with a given slew rate into an intermediate voltage waveform;

instructions to characterize parasitic capacitances of the standard cell; and

instructions to characterize the standard cell for an output current for a driving stage of the multi-CCC current source model.

32. The computer readable product of claim 31, wherein the instructions stored in the computer readable storage device further include:

instructions to characterize the standard cell for a miller capacitance coupled between the transform stage and the driving stage of the multi-CCC current source model.

33. The computer readable product of claim 32, wherein

the instructions to characterize the standard cell for the miller capacitance includes

instructions to simulate circuits including transistors in the standard cell using a transistor level circuit simulator,

instructions to hold the output of the standard cell to a constant output voltage with a voltage source coupled to the output of the standard cell,

instructions to switch one input of the standard cell using a ramp input signal waveform with a fast slew rate,

instructions to measure the output current into the voltage source to determine a miller current and a switching delay time,

instructions to estimate a change in voltage over a time period in the miller capacitance, and

instructions to calculate the miller capacitance in response to the miller current and the change in voltage over the time period in the miller capacitance.