Wake-and-go mechanism for a data processing system

• US 8,516,484 B2
• Filed: 02/01/2008
• Issued: 08/20/2013
• Est. Priority Date: 02/01/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi K., Sharma, Satya P., Swanberg, Randal C.
• Primary Examiner(s): Puente, Emerson
• Assistant Examiner(s): SWIFT, CHARLES M
• Application Number:
  US12/024,466
• Publication Number:
  US 20110173631A1
• Time in Patent Office: 2,027 Days
• Field of Search: None
• US Class Current: 718/100
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/542 Event management; Broadcasting; Multicasting; Notifications

Abstract

A wake-and-go mechanism is provided for a data processing system. When a thread is waiting for an event, rather than performing a series of get-and-compare sequences, the thread updates a wake-and-go array with a target address associated with the event. The thread then goes to sleep until the event occurs. The wake-and-go array may be a content addressable memory (CAM). When a transaction appears on the symmetric multiprocessing (SMP) fabric that modifies the value at a target address in the CAM, the CAM returns a list of storage addresses at which the target address is stored. The operating system or a background sleeper thread associates these storage addresses with the threads waiting for an even at the target addresses, and may wake the one or more threads waiting for the event.

Claims

1. A method, in a data processing system, for performing a wake-and-go operation, the method comprising:

detecting a thread that is waiting for an event that modifies a data value associated with a target address;

storing the target address in a wake-and-go entry of a content addressable memory in association with a thread identifier of the thread;

placing the thread in a sleep state;

responsive to detecting a write to the target address, using the target address to address the content addressable memory and returning, by the content addressable memory, a storage address of the wake-and-go entry; and

placing the thread corresponding to the thread identifier in the wake-and-go entry in a non-sleep state; and

responsive to the thread determining the data value being written to the target address is not the data value for which the thread is waiting, storing the target address in a wake-and-go entry of the content addressable memory in association with the thread identifier of the thread and placing the thread in a sleep state.

2. The method of claim 1, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

3. The method of claim 1, wherein detecting a thread that is waiting for an event that modifies a data value associated with a target address comprises:

detecting that the thread executes a specialized processor instruction to update the wake-and-go storage array.

4. The method of claim 1, wherein detecting a thread that is waiting an event that modifies a data value associated with a target address comprises:

detecting that the thread makes a call to an operating system to update the wake-and-go array.

5. The method of claim 1, wherein detecting a thread that is waiting an event that modifies a data value associated with a target address comprises:

detecting that the thread makes a call to a background sleeper thread to update the wake-and-go storage array.

6. The method of claim 5, wherein the background sleeper thread performs the step of determining whether to wake the thread.

7. The method of claim 1, wherein the method is performed by a wake-and-go mechanism.

8. The method of claim 7, wherein the wake-and-go mechanism is one of a hardware component within a processor, a hardware component associated with the wake-and-go storage array, or a hardware component associated with a system bus.

9. A data processing system, comprising:

A hardware wake-and-go mechanism; and

a wake-and-go storage array,

wherein the wake-and-go mechanism is configured to;

detect a thread that is waiting for an event that modifies a data value associated with a target address;

store the target address in a wake-and-go entry of a content addressable memory in association with a thread identifier of the thread;

place the thread in a sleep state;

responsive to detecting a write to the target address, use the target address to address the content addressable memory and return, by the content addressable memory, a storage address of the wake-and-go entry;

place the thread corresponding to the thread identifier in the wake-and-go entry in a non-sleep state; and

responsive to the thread determining the data value being written to the target address is the data value for which the thread is waiting, store the target address in a wake-and-go entry of the content addressable memory in association with the thread identifier of the thread and placing the thread in a sleep state.

10. The data processing system of claim 9, wherein detecting a thread that is waiting for an event that modifies a data value associated with a target address comprises:

detecting that the thread executes a specialized processor instruction to update the wake-and-go storage array.

11. The data processing system of claim 9, wherein the event is an asynchronous event caused by a device outside a processor running the thread.

12. The data processing system of claim 9, wherein detecting a thread that is waiting an event that modifies a data value associated with a target address comprises:

detecting that the thread makes a call to an operating system to update the wake-and-go array.

13. The data processing system of claim 9, wherein the wake-and-go mechanism is one of a hardware component within a processor, a hardware component associated with the wake-and-go storage array, or a hardware component associated with a system bus.

14. A computer program product comprising a non-transitory computer readable storage medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

detect a thread that is waiting for an event that modifies a data value associated with a target address;

store the target address in a wake-and-go entry of a content addressable memory in association with a thread identifier of the thread;

place the thread in a sleep state;

responsive to detecting a write to the target address, using the target address to address the content addressable memory and return, by the content addressable memory, a storage address of the wake-and-go entry;

place the thread corresponding to the thread identifier in the wake-and-go entry in a non-sleep state; and

responsive to the thread determining the data value being written to the target address is not the data value for which the thread is waiting, store the target address in a wake-and-go entry of the content addressable memory in association with the thread identifier of the thread and place the thread in a sleep state.

15. The computer program product of claim 14, wherein detecting a thread that is waiting for an event that modifies a data value associated with a target address comprises:

detecting that the thread executes a specialized processor instruction to update the wake-and-go storage array.

16. The computer program product of claim 14, wherein detecting a thread that is waiting for an event that modifies a data value associated with a target address comprises:

detecting that the thread makes a call to an operating system to update the wake-and-go storage array.

17. The computer program product of claim 14, wherein detecting a thread that is waiting for an event that modifies a data value associated with a target address comprises:

detecting that the thread makes a call to a background sleeper thread to update the wake-and-go storage array.

18. The computer program product of claim 14, wherein the event is an asynchronous event caused by a device outside a processor running the thread.