Ultrathin porous nanoscale membranes, methods of making, and uses thereof

• US 8,518,276 B2
• Filed: 04/20/2012
• Issued: 08/27/2013
• Est. Priority Date: 04/29/2005
• Status: Active Grant

• Current Assignee: University of Rochester
• Original Assignee: University of Rochester
• Inventors: Striemer, Christopher C., Fauchet, Philippe M., Gaborski, Thomas R., McGrath, James L.
• Primary Examiner(s): BASS, DIRK R
• Application Number:
  US13/452,453
• Publication Number:
  US 20120267337A1
• Time in Patent Office: 494 Days
• Field of Search: 210/650, 210/500.25, 210/506, 210/646, 210/321.84, 216/56, 216/2, 96/4, 95/45, 435/4
• US Class Current: 216/2
• CPC Class Codes: B01D 2325/08 Patterned membranes
• CPC Class Codes: B01D 2325/14 Membrane materials having negatively charged functional groups
• CPC Class Codes: B01D 2325/26 Electrical properties
• CPC Class Codes: B01D 57/02 by electrophoresis treatment of water, waste water, sewage or sludge by electrophoresis C02F1/469; electrophoretic production of compounds or non-metals C25B7/00; investigating or analysing materials by using electrophoresis G01N27/26
• CPC Class Codes: B01D 61/18 Apparatus therefor
• CPC Class Codes: B01D 61/28 Apparatus therefor
• CPC Class Codes: B01D 67/0062 by micromachining techniques, e.g. using masking and etching steps, photolithography
• CPC Class Codes: B01D 67/0072 by deposition from the gaseous phase, e.g. sputtering, CVD, PVD
• CPC Class Codes: B01D 71/0213 Silicon
• CPC Class Codes: B01L 2300/0819 Microarrays; Biochips
• CPC Class Codes: B01L 2400/0472 Diffusion
• CPC Class Codes: B01L 2400/0627 Molecular gates forcing or inhibiting diffusion
• CPC Class Codes: B01L 3/50255 Multi-well filtration
• CPC Class Codes: H01J 2237/20 Positioning, supporting, modifying or maintaining the physical state of objects being observed or treated
• CPC Class Codes: H01M 2250/00 Fuel cells for particular applications; Specific features of fuel cell system
• CPC Class Codes: H01M 2300/0094 in the form of layered products, e.g. coatings
• CPC Class Codes: H01M 4/94 Non-porous diffusion electrodes, e.g. palladium membranes, ion exchange membranes
• CPC Class Codes: H01M 8/1037 having silicon, e.g. sulfonated crosslinked polydimethylsiloxanes
• CPC Class Codes: H01M 8/1076 Micromachining techniques, e.g. masking, etching steps or photolithography
• CPC Class Codes: Y02E 60/50 Fuel cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A process for forming a porous nanoscale membrane is described. The process involves applying a nanoscale film to one side of a substrate, where the nanoscale film includes a semiconductor material; masking an opposite side of the substrate; etching the substrate, beginning from the masked opposite side of the substrate and continuing until a passage is formed through the substrate, thereby exposing the film on both sides thereof to form a membrane; and then simultaneously forming a plurality of randomly spaced pores in the membrane. The resulting porous nanoscale membranes, characterized by substantially smooth surfaces, high pore densities, and high aspect ratio dimensions, can be used in filtration devices, microfluidic devices, fuel cell membranes, and as electron microscopy substrates.

Claims

1. A method of producing a porous nanoscale membrane comprising:

applying a multilayered film to one side of a substrate, the multilayered film comprising a nanoscale film between sacrificial films wherein the nanoscale film comprises an amorphous semiconductor material;

masking an opposite side of the substrate;

etching the substrate, beginning from the masked opposite side of the substrate and continuing until a passage is formed through the substrate, thereby exposing the film on both sides thereof to form a membrane; and

converting the amorphous semiconductor material, before or after said etching, to a crystalline semiconductor material and thereby forming a plurality of spaced pores in the nanoscale film during said converting to produce the porous nanoscale membrane.

2. The method according to claim 1 wherein said applying a multilayered film comprises applying a first sacrificial film to the one side of the substrate, applying the nanoscale film over the first sacrificial film, and applying a second sacrificial film over the nanoscale film.

3. The method according to claim 2 wherein said applying the nanoscale film and said applying the first and second sacrificial films are carried out in a manner to form substantially planar films.

4. The method according to claim 2 wherein said applying the nanoscale film and said applying the first and second sacrificial films are carried out in a manner to form a relief-patterned films.

5. The method according to claim 1 wherein each sacrificial film is an oxide film.

6. The method according to claim 1 wherein said converting is carried out by annealing the amorphous semiconductor material at a temperature and duration suitable to induce crystallization.

7. The method according to claim 1 wherein the crystalline semiconductor material is in the form of a polycrystalline or a nanocrystalline material.

8. The method according to claim 5 wherein each oxide film is silicon dioxide and the substrate is silicon.

9. The method according to claim 8 wherein said masking comprises forming an incomplete silicon dioxide film on the opposite side of the silicon substrate.

10. The method according to claim 9 wherein said etching is carried out using an etchant that has a silicon/silicon dioxide selectivity that is greater than about 10,000.

11. The method according to claim 9 wherein said etching is carried out using an etchant comprising ethylenediamine, pyrocatechol, pyrazine, and water.

12. The method according to claim 1 further comprising:

removing the sacrificial films after said etching.

13. The method according to claim 12 wherein said removing is carried out after said converting.

14. The method according to claim 12 wherein said removing comprises exposing the sacrificial films to a buffered oxide etchant solution, or a hydrofluoric acid etchant solution.

15. The method according to claim 1 wherein said etching is carried out in a container that exposes substrate to etchant solution only from the masked opposite side thereof.

16. The method according to claim 1 further comprising:

heating and/or stirring etchant solution during said etching.

17. The method according to claim 1 wherein said applying comprises radio-frequency magnetron sputtering, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, thermal chemical growth, radio frequency sputtering, DC sputtering, thermal evaporation, electron beam evaporation, or electroplating.

18. The method according to claim 1 wherein said applying further comprises changing conditions during film deposition, the conditions being selected from the group of pressure changes, plasma density changes, plasma power changes, temperature changes, source material changes, and gas composition changes.

19. The method according to claim 1 wherein the semiconductor material is undoped silicon or germanium, p-doped silicon or germanium, n-doped silicon or germanium, or a silicon-germanium alloy.

20. A method of producing a porous nanoscale membrane comprising:

providing a substrate having a multilayered film formed on one side of the substrate and a mask formed on an opposite side of the substrate, the multilayered film comprising a nanoscale film between sacrificial films wherein the nanoscale film comprises an amorphous semiconductor material;

etching the substrate, beginning from the masked opposite side of the substrate and continuing until a passage is formed through the substrate, thereby exposing the film on both sides thereof to form a membrane;

annealing the amorphous semiconductor material, before or after said etching, under conditions effective to convert the amorphous semiconductor material into a crystalline semiconductor material having a plurality of spaced pores in the nanoscale film; and

removing the sacrificial films to produce a porous nanoscale membrane exposed on both sides thereof.

21. The method according to claim 20 wherein said applying the nanoscale film and said applying the sacrificial film is carried out in a manner to form substantially planar films.

22. The method according to claim 21, wherein the porous nanoscale membrane has a surface roughness of less than 1 nm on both sides thereof.

23. The method according to claim 20 wherein each sacrificial film is an oxide film.

24. The method according to claim 23 wherein each oxide film is silicon dioxide and the substrate is silicon.

25. The method according to claim 24 wherein the mask comprises an incomplete silicon dioxide film formed on the opposite side of the silicon substrate.

26. The method according to claim 25 wherein said etching is carried out using an etchant that has a silicon/silicon dioxide selectivity that is greater than about 10,000.

27. The method according to claim 25 wherein said etching is carried out using an etchant comprising ethylenediamine, pyrocatechol, pyrazine, and water.

28. The method according to claim 20 wherein said annealing is carried out at a temperature and duration suitable to induce crystallization.

29. The method according to claim 20 wherein the crystalline semiconductor material is in the form of a polycrystalline or a nanocrystalline material.

30. The method according to claim 20 wherein said removing comprises exposing the sacrificial films to a buffered oxide etchant solution, or a hydrofluoric acid etchant solution.

31. The method according to claim 20 wherein the semiconductor material is undoped silicon or germanium, p-doped silicon or germanium, n-doped silicon or germanium, or a silicon-germanium alloy.