Method for forming accumulation-mode field effect transistor with improved current capability
First Claim
1. A method of forming an accumulation-mode field effect transistor, the method comprising:
- forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type, the channel region extending from a top surface of the semiconductor region to a first depth within the semiconductor region;
forming a gate trench in the semiconductor region, the gate trench extending from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth; and
forming a silicon region of a second conductivity type in the semiconductor region and extending to a third depth of at least the second depth such that the silicon region forms a P-N junction with the channel region along a wall of the silicon region.
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Abstract
A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.
344 Citations
14 Claims
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1. A method of forming an accumulation-mode field effect transistor, the method comprising:
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forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type, the channel region extending from a top surface of the semiconductor region to a first depth within the semiconductor region; forming a gate trench in the semiconductor region, the gate trench extending from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth; and forming a silicon region of a second conductivity type in the semiconductor region and extending to a third depth of at least the second depth such that the silicon region forms a P-N junction with the channel region along a wall of the silicon region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification