Methods of forming a plurality of capacitors

• US 8,518,788 B2
• Filed: 08/11/2010
• Issued: 08/27/2013
• Est. Priority Date: 08/11/2010
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Che-Chi
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US12/854,446
• Publication Number:
  US 20120040507A1
• Time in Patent Office: 1,112 Days
• Field of Search: 438/253, 438/255, 438/239, 438/238, 438/381, 257/E21.657, 257/E21.658, 257/E21.66
• US Class Current: 438/381
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/87 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors.

Claims

1. A method of forming a plurality of capacitors, comprising:

providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials;

anisotropically etching openings to extend through the outer insulative retaining material and the second material;

after the anisotropic etching, isotropically etching remaining of the second material through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials, the isotropic etching of the second material being conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials; and

incorporating the capacitor electrodes into a plurality of capacitors.

2. The method of claim 1 wherein the inner insulative retaining material and the outer insulative retaining material are of the same composition.

3. The method of claim 1 wherein the first material comprises polysilicon.

4. The method of claim 1 wherein the second material comprises an insulator.

5. The method of claim 1 wherein the first and second materials are of different compositions, the first material comprising polysilicon, the second material comprising an insulator.

6. The method of claim 5 wherein the second material comprises silicon dioxide.

7. The method of claim 1 wherein the anisotropic etching is conducted to extend the openings through the inner insulative retaining material to the first material.

8. The method of claim 7 wherein the first and second materials are of different compositions, the isotropic etching of the second material being conducted selectively relative to first material.

9. The method of claim 7 comprising after isotropically etching the second material, isotropically etching the first material through the openings selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials.

10. The method of claim 1 wherein the plurality of capacitor electrodes are fabricated within a capacitor array area, the substrate comprising a circuitry area immediately adjacent the capacitor array area, the substrate being void of a separating trench that is elevationally coincident with the capacitor electrodes between said capacitor array area and said immediately adjacent circuitry area.

11. A method of forming a plurality of capacitors, comprising:

providing a substrate comprising a capacitor array area and a circuitry area immediately adjacent the capacitor array area, the capacitor array area comprising a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, a second insulative material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials, the inner and outer insulative retaining materials and the second insulative material extending laterally continuously from the capacitor array area into said immediately adjacent circuitry area, immediately adjacent pairs of capacitor electrodes having a first maximum spacing there-between, the immediately adjacent circuitry area comprising a conductive structure which is closest to an immediately adjacent one of the capacitor electrodes at a second minimum spacing, the second minimum spacing being greater than the first maximum spacing;

anisotropically etching openings within the capacitor array area to extend through the outer insulative retaining material and the second insulative material;

after the anisotropic etching, conducting a timed isotropic etch through the openings within the capacitor array area which is long enough to remove all remaining second insulative material received along said first maximum spacing between said immediately adjacent pairs of capacitor electrodes and which is short enough to leave some second insulative material between said conductive structure and said closest capacitor electrode along said second minimum spacing, the timed isotropic etching of the second insulative material being conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials; and

incorporating the capacitor electrodes into a plurality of capacitors.

12. The method of claim 11 wherein the second minimum spacing is at least two times greater than the first maximum spacing.

13. The method of claim 11 wherein the first material does not extend laterally continuously from the capacitor array area into said immediately adjacent circuitry area.

14. The method of claim 11 wherein second insulative material is received elevationally inward of the inner insulative retaining material within said immediately adjacent circuitry area.

15. The method of claim 11 wherein the first material does not extend laterally continuously from the capacitor array area into said immediately adjacent circuitry area, first material and second insulative material being received elevationally inward of the inner insulative retaining material within said immediately adjacent circuitry area.

16. The method of claim 11 wherein the first material and the second insulative materials are of different compositions, the first material comprising polysilicon, the second insulative material comprising silicon dioxide.

17. The method of claim 11 wherein the first material and the second insulative material are of different compositions, the anisotropic etching is conducted to extend the openings through the inner insulative retaining material to the first material, and the isotropic etching of the second insulative material is conducted selectively relative to the first material.

18. The method of claim 17 comprising after isotropically etching the second insulative material, isotropically etching the first material through the openings selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials.

19. A method of forming a plurality of capacitors, comprising:

providing a substrate comprising a capacitor array area and a circuitry area immediately adjacent the capacitor array area, the immediately adjacent circuitry area having a first opening received within an insulating material;

depositing a first material over the capacitor array area and within the first opening in the immediately adjacent circuitry area;

depositing an elevationally inner insulative retaining material over the first material within the capacitor array area and over the insulating material and first material within the first opening in the immediately adjacent circuitry area;

depositing a second insulative material over the inner insulative retaining material within the capacitor array area and the immediately adjacent circuitry area, the first material and the second insulative material being of different compositions;

depositing an elevationally outer insulative retaining material over the second insulative material within the capacitor array area and the immediately adjacent circuitry area;

in a common masking step, forming a plurality of capacitor storage node openings within the capacitor array area and forming a second opening within the immediately adjacent circuitry area, the second opening overlapping at least some of the first opening, the capacitor storage node openings and the second opening extending through the outer insulative retaining material and the second insulative material, the capacitor storage node openings extending through the first material within the capacitor array area, the second opening extending through the first material within the first opening in the immediately adjacent circuitry area;

depositing conductive material within the capacitor storage node openings in the capacitor array area and within the second opening in the immediately adjacent circuitry area;

anisotropically etching openings within the capacitor array area to extend through the outer insulative retaining material, the second insulative material, and the inner insulative retaining material to the first material;

after the anisotropic etching, isotropically etching remaining of the second insulative material through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials within the capacitor array area, the isotropic etching of the second material being conducted selectively relative to the conductive material, the inner and outer insulative retaining materials, and the first material;

after isotropically etching the second material, isotropically etching the first material through the openings selectively relative to the conductive material, the inner and outer insulative retaining materials, and the insulating material;

incorporating the conductive material within the capacitor array area into a plurality of capacitors.

20. The method of claim 19 wherein the common masking step comprises forming a hardmask elevationally over the outer insulative retaining material within the capacitor array area and the immediately adjacent circuitry area;

said hard-mask comprising the second insulative material, the first material over the second material, and the outer insulative retaining material over the second material.

21. The method of claim 19 wherein the first material is thicker than the second insulative material.

22. The method of claim 19 wherein the insulating material and the second insulative material are of the same composition.

23. The method of claim 19 wherein the conductive material is deposited to completely fill the capacitor storage node openings and less than fill the second opening.

24. The method of claim 23 wherein the conductive material is deposited to form a sidewall lining within the second opening.

25. The method of claim 19 wherein,

the inner and outer insulative retaining materials and the second material extend laterally continuously from the capacitor array area into said immediately adjacent circuitry area, immediately adjacent pairs of capacitor electrodes having a first maximum spacing there-between, the conductive material within the second opening in the immediately adjacent circuitry area comprising a conductive structure which is closest to an immediately adjacent one of the capacitor electrodes at a second minimum spacing, the second minimum spacing being greater than the first maximum spacing;

and

said isotropically etching of the second insulative material being conducted as a timed isotropic etch through the openings within the capacitor array area which is long enough to remove all remaining second insulative material received along said first maximum spacing between said immediately adjacent pairs of capacitor electrodes and which is short enough to leave some second insulative material between said conductive structure and said closest capacitor electrode along said second minimum spacing.

26. The method of claim 25 wherein the second minimum spacing is at least two times greater than the first maximum spacing.

27. The method of claim 19 wherein the first material comprises polysilicon and the second insulative material comprises silicon dioxide.