Semiconductor devices and methods of forming thereof
First Claim
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1. A semiconductor device comprising:
- a substrate;
an active layer on the substrate;
a capping layer on the active layer;
source/drain electrodes on the capping layer;
a gate electrode on the active layer;
a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall;
a first insulation layer on the capping layer, a second insulation layer on the first insulation layer; and
a third insulation layer spaced apart from the first insulation layer, with the second insulation layer therebetween,wherein the first void region includes a first void upper region on the first insulation layer and a first void lower region below the first insulation layer,wherein the gate electrode comprises a gate foot contacting the active layer and a gate head on the gate foot, and a width of the gate head is broader than a width of the gate foot,wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers, andwherein the second void region is defined by a space between the third insulation layer and the active layer, the second void region extends from the active layer to the third insulation layer without discontinuity, and the second void region has an upper end in contact with the third insulation layer and a lower end in contact with the active layer.
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Abstract
Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.
33 Citations
18 Claims
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1. A semiconductor device comprising:
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a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall; a first insulation layer on the capping layer, a second insulation layer on the first insulation layer; and a third insulation layer spaced apart from the first insulation layer, with the second insulation layer therebetween, wherein the first void region includes a first void upper region on the first insulation layer and a first void lower region below the first insulation layer, wherein the gate electrode comprises a gate foot contacting the active layer and a gate head on the gate foot, and a width of the gate head is broader than a width of the gate foot, wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers, and wherein the second void region is defined by a space between the third insulation layer and the active layer, the second void region extends from the active layer to the third insulation layer without discontinuity, and the second void region has an upper end in contact with the third insulation layer and a lower end in contact with the active layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of forming a semiconductor device, the method comprising:
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preparing a substrate; sequentially forming an active layer and a capping layer on the substrate; forming source/drain electrodes on the capping layer; forming a first insulation layer on the source/drain electrodes; exposing the capping layer by etching a portion of the first insulation layer; sequentially forming a second and a third insulation layers on the capping layer and the first insulation layer; forming an opening exposing a portion of the second insulation layer by etching a portion of the third insulation layer; forming a first recess exposing the capping layer by etching the second insulation layer through the opening; forming a second recess exposing the active layer by etching the capping layer; and forming in the opening a gate electrode connected to the active layer, wherein a void region is defined by a space between the third insulation layer and the active layer, the second void region extends from the active layer to the third insulation layer without discontinuity, and the void region has an upper end in contact with the third insulation layer and a lower end in contact with the active layer. - View Dependent Claims (11, 12, 13, 14)
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15. A method of forming a semiconductor device, the method comprising:
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preparing a substrate; sequentially forming an active layer and a capping layer on the substrate; forming source/drain electrodes on the capping layer; forming a first insulation layer on the source/drain electrodes; exposing the capping layer by etching a portion of the first insulation layer; sequentially forming a second and a third insulation layers on the capping layer and the first insulation layer; forming an opening exposing a portion of the second insulation layer by etching a portion of the third insulation layer; forming a first recess exposing the capping layer by etching the second insulation layer through the opening; forming a second recess exposing the active layer by etching the capping layer; and forming in the opening a gate electrode connected to the active layer, wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers, wherein the etching of the portion of the third insulation layer is performed using an anisotropic etching process, and wherein the anisotropic etching process uses an etching recipe having a higher etching rate with respect to the third insulation layer than the second insulation layer.
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16. A method of forming a semiconductor device, the method comprising:
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preparing a substrate; sequentially forming an active layer and a capping layer on the substrate; forming source/drain electrodes on the capping layer; forming a first insulation layer on the source/drain electrodes; exposing the capping layer by etching a portion of the first insulation layer; sequentially forming a second and a third insulation layers on the capping layer and the first insulation layer; forming an opening exposing a portion of the second insulation layer by etching a portion of the third insulation layer; forming a first recess exposing the capping layer by etching the second insulation layer through the opening; forming a second recess exposing the active layer by etching the capping layer; and forming in the opening a gate electrode connected to the active layer, wherein the second insulation layer has an etch selectivity with respect to the first and third insulation layers, and wherein the exposing of the capping layer by etching the second insulation layer through the opening is performed using an isotropic etching process. - View Dependent Claims (17)
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18. A semiconductor device comprising:
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a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall; a first insulation layer on the capping layer, a second insulation layer on the first insulation layer; and a third insulation layer spaced apart from the first insulation layer, with the second insulation layer therebetween, wherein the second void region is defined by a space between the third insulation layer and the active layer, the second void region extends from the active layer to the third insulation layer without discontinuity, and the second void region has an upper end in contact with the third insulation layer and a lower end in contact with the active layer.
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Specification