Modified design rules to improve device performance

• US 8,519,444 B2
• Filed: 09/10/2010
• Issued: 08/27/2013
• Est. Priority Date: 09/10/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lum, Annie, Tao, Derek C., Lee, Cheng Hung, Lu, Chung-Ji, Cheng, Hong-Chen, Agrawal, Vineet Kumar, Kim, Keun-Young, Cho, Pyong Yun
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US12/879,447
• Publication Number:
  US 20120061764A1
• Time in Patent Office: 1,082 Days
• Field of Search: 257/201, 257/202, 257/E27.108, 257/203, 257/401
• US Class Current: 257/202
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.

Claims

1. A device region on a substrate, comprising:

an edge device, wherein the edge device has at least one device on one side;

a dummy device next to the edge device, wherein the dummy device is on the opposite side of the edge device from the at least one device, and wherein the dummy device shares a first diffusion region with the edge device and a second diffusion region is formed at an opposite side of the dummy device; and

a dummy gate structure next to the dummy device, wherein the dummy device is between the dummy gate structure and the edge device, and the dummy gate structure does not overlap the second diffusion region.

2. The device region of claim 1, wherein the edge device and the dummy device are NMOS (N-type metal-oxide-semiconductor) devices.

3. The device region of claim 2, wherein the gate structure of the dummy device is tied to Vss to deactivate the dummy device.

4. The device region of claim 1, wherein the edge device and the dummy device are PMOS (P-type metal-oxide-semiconductor) devices.

5. The device region of claim 4, wherein the gate structure of the dummy device is tied to Vdd to deactivate the dummy device.

6. The device region of claim 1, wherein a gate length of at least one of the edge device, the dummy device and the at least one device is less than 35 nm.

7. The device region of claim 1, wherein a gate structure of the dummy gate is considered as a dummy gate structure according to a design rule.

8. A device region on a substrate, comprising:

a first device with a first gate length;

a second device with a second gate length, wherein the second gate length is different from the first gate length; and

a dummy device between the first device and the second device, wherein there is no other device between the first device and the dummy device and no other device between the second device and the dummy device, wherein the dummy device shares a first diffusion region with the first device and a second diffusion region with the second device, wherein a gate length of the dummy device is longer than at least one of a gate length of the first device or a gate length of the second device.

9. The device region of claim 8, wherein the first device, the second device, and the dummy device are all NMOS (N-type metal-oxide-semiconductor) devices.

10. The device region of claim 9, wherein a gate structure of the dummy device is tied to Vss to deactivate the dummy device.

11. The device region of claim 8, wherein the first device, the second device, and the dummy device are all PMOS (P-type metal-oxide-semiconductor) devices.

12. The device region of claim 11, wherein a gate structure of the dummy device is tied to Vdd to deactivate the dummy device.

13. The device region of claim 8, wherein a gate length of the first device and a gate length of the second device are less than 35 nm.

14. A device region on a substrate, comprising:

a first device with a non-rectangular diffusion region on one side;

a second device with a diffusion region near the first device, wherein a width of the diffusion region of the second device does not equal one and more widths of the non-rectangular diffusion region of the first device; and

a dummy device between the first device and the second device, wherein there is no other device between the first device and the dummy device and no other device between the second device and the dummy device, wherein the dummy device shares the non-rectangular diffusion region with the first device and the diffusion region of the second device near the first device.

15. The device region of claim 14, wherein the first device, the second device, and the dummy device are all NMOS (N-type metal-oxide-semiconductor) devices.

16. The device region of claim 15, wherein a gate structure of the dummy device is tied to Vss to deactivate the dummy device.

17. The device region of claim 14, wherein the first device, the second device, and the dummy device are PMOS (P-type metal-oxide-semiconductor) devices.

18. The device region of claim 17, wherein a gate structure of the dummy device is tied to Vdd to deactivate the dummy device.

19. The device region of claim 17, wherein a gate length of the first device and a gate length of the second device are less than 35 nm.