Poly profile engineering to modulate spacer induced stress for device enhancement

• US 8,519,445 B2
• Filed: 07/14/2011
• Issued: 08/27/2013
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Ho, Vincent, Lin, Wenhe, Teh, Young Way, Siew, Yong Kong, Zhang, Bei Chao, Zhang, Fan, Sheng, Haifeng, Tan, Juan Boon
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US13/182,455
• Publication Number:
  US 20110266628A1
• Time in Patent Office: 775 Days
• Field of Search: 438/197, 438/199, 438/301, 438/303, 438/305, 438/306, 438/308, 257/204, 257/369, 257/401, 257/E21.632
• US Class Current: 257/204
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate

Abstract

The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Claims

1. A device comprising:

a substrate defined with a first transistor region for a first transistor of a first type and a second transistor region for a second transistor of a second type, the substrate is prepared with

a first gate of the first transistor being disposed in the first transistor region,

a second gate of the second transistor being disposed in the second transistor region,

the first gate includes first doped ions and expands at a first target region which is less than a total thickness of the first gate, and

the second gate includes second doped ions and expands at a second target region which is less than a total thickness of the second gate, wherein the first target region is in a different portion of the gate than the second target region.

2. The device of claim 1 wherein the first target region is in an upper portion of the first gate.

3. The device of claim 2 wherein the first transistor is a p-type transistor.

4. The device of claim 1 wherein the first doped ions comprise Ge or Xe or a combination thereof.

5. The device of claim 1 wherein the expansion at the second target region causes a channel of the second transistor in the substrate under the second gate to have a second stress to improve dopant mobility of the second transistor.

6. The device of claim 5 wherein:

the first target region is in a lower portion of the first gate; and

the second target region is in an upper portion of the second gate.

7. The device of claim 5 wherein:

the expansion at the first target region causes a channel of the first transistor in the substrate under the first gate to have a first stress to improve dopant mobility of the first transistor, wherein the first transistor is a n-type transistor and the first stress is a tensile stress; and

the second transistor is a p-type transistor and the second stress is a compressive stress.

8. The device of claim 5 wherein the first and second doped ions comprise Ge or Xe or a combination thereof.

9. The device of claim 8 wherein the first and second doped ions comprise the same type of ions.

10. A device comprising:

a substrate defined with a transistor region for a transistor, the substrate is prepared with

a gate of the transistor being disposed in the transistor region, and

the gate includes doped ions and expands at a target region of the gate, wherein the expansion of the gate causes a stress to be applied to a channel of the transistor under the gate, the transistor is a n-type transistor and the gate has sidewalls having a lower portion and a distance between the sidewalls at the lower portion of the gate is increased.

11. The device of claim 10 wherein the expansion of the gate includes upward forces on the substrate adjacent to the gate.

12. A device comprising:

a substrate, the substrate includes first transistor region for a first transistor of a first type and a second transistor region for a second transistor of a second type, the substrate is prepared with

a first gate of the first transistor being disposed in the first transistor region,

a second gate of the second transistor being disposed in the second transistor region,

the first gate includes first doped ions at a first target region which is less than a total thickness of the first gate,

the second gate includes second doped ions at a second target region which is less than a total thickness of the second gate, wherein the first target region is in a different portion of the gate than the second target region,

the first target region of the first gate expands to cause a channel of the first transistor in the substrate under the first gate to have a first stress to improve dopant mobility of the first transistor, and

the second target region of the second gate expands to cause a channel of the second transistor in the substrate under the second gate to have a second stress to improve dopant mobility of the second transistor.

13. The device of claim 12 wherein:

the first target region comprises a lower portion of the first gate; and

the second target region comprises an upper portion of the second gate.

14. The device of claim 12 wherein:

the first target region comprises a lower portion of the first gate;

the first stress comprises a tensile stress;

the second target region comprises an upper portion of the second gate; and

the second stress comprises a compressive stress.

15. The device of claim 14 wherein:

the first type comprises n-type; and

the second type comprises p-type.

16. The device of claim 12 wherein the first doped ions comprise Ge or Xe or a combination thereof.

17. The device of claim 12 wherein the second doped ions comprise Ge or Xe or a combination thereof.

18. The device of claim 12 wherein the first target region is in a lower portion of the first gate.

19. The device of claim 18 wherein the first transistor is a n-type transistor and the first stress is a tensile stress.

20. The device of claim 12 wherein the first and second doped ions comprise the same type of ions.