6F2 DRAM cell

• US 8,519,462 B2
• Filed: 06/27/2011
• Issued: 08/27/2013
• Est. Priority Date: 06/27/2011
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wang, Yih, Webb, M. Clair, Lindert, Nick, Sivakumar, Swaminathan, Zhang, Kevin X., Somasekhar, Dinesh
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US13/169,864
• Publication Number:
  US 20120326218A1
• Time in Patent Office: 792 Days
• Field of Search: 257/296, 257/298, 257/401, 257/E27.084, 438/241
• US Class Current: 257/298
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A 6F² DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.

Claims

1. A DRAM array comprising:

a pair of cells, each cell comprising an access transistor having n-type source/drain regions defining a channel region, and a capacitor, one source/drain region of each access transistor in a first pair of cells being connected to a common via contact providing a connection to a bit line, the other source/drain region of each access transistor being separated from other source/drain regions of access transistors of adjacent pairs of cells by common channel regions defined by the n-type source/drain regions;

access word lines extending generally perpendicular to the bit line, each access word line extending over a channel region of an access transistor, the access word lines comprising a material with a work function favoring n-channel devices; and

dummy word lines extending generally perpendicular to the bit line, each dummy word line extending over one of the common channel regions, the dummy word lines comprise a material with a work function favoring p-channel devices.

2. The DRAM array of claim 1, wherein the work function for the dummy word lines is approximately 4.8-5.1 eV.

3. The DRAM array of claim 1, wherein the dummy word lines are coupled to a negative potential with respect to a substrate potential.

4. The DRAM array of claim 1, including via contacts connected to the other source/drain regions of the access transistors for providing a connection to overlying capacitors.

5. The DRAM array of claim 1, wherein the bit line is a metal line disposed above the pairs of cells in the array.

6. The DRAM array of claim 1, wherein the capacitors are disposed above the bit lines.

7. The DRAM array of claim 1, wherein the channel regions of the access transistors are angled with respect to their source/drain regions.

8. The DRAM array of claim 1, wherein the source/drain regions, access transistor channel regions, and common channel regions are formed from a continuous serpentine-shaped semiconductor body disposed generally perpendicular to the word lines.

9. The DRAM array of claim 1, wherein each cell has an area of approximately 6F².

10. The DRAM array of claim 1, wherein the channel regions of the access transistors are angled with respect to their source/drain regions.

11. The DRAM array of claim 1, wherein the source/drain regions, access transistor channel regions, and common channel regions are formed from a continuous serpentine-shaped semiconductor body disposed generally perpendicular to the word lines.