Semiconductor device

• US 8,519,487 B2
• Filed: 03/21/2011
• Issued: 08/27/2013
• Est. Priority Date: 03/21/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Huang, Wei-Hang
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US13/052,115
• Publication Number:
  US 20120241873A1
• Time in Patent Office: 890 Days
• Field of Search: 257/310, 257/410, 438/595
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer; and a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer.

Claims

1. A semiconductor device, comprising:

a substrate;

a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer, wherein the high-k dielectric layer is U-shaped;

a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer and a first spacer, and is non-L-shaped; and

a second seal layer disposed on a sidewall of the first spacer, wherein the second seal layer comprises a material different from the first seal layer, and the second seal layer comprises an L-shaped seal layer.

2. The semiconductor device of claim 1, wherein the etching rate of the second seal layer is different from the etching rate of the first seal layer.

3. The semiconductor device of claim 1, further comprising a second spacer disposed on the second seal layer.

4. The semiconductor device of claim 1, wherein the gate structure comprises:

a gate insulating layer;

the high-k dielectric layer disposed on the gate insulating layer; and

a polysilicon gate disposed on the high-k dielectric layer.

5. The semiconductor device of claim 1, wherein the gate structure comprises:

a gate insulating layer;

the high-k dielectric layer disposed on the gate insulating layer; and

a metal gate disposed on the high-k dielectric layer.

6. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming a first seal layer on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer and a first spacer, and is non-L-shaped;

forming a lightly doped drain in the substrate adjacent to two sides of the gate structure;

forming a L-shaped second seal layer on a sidewall of the first spacer, wherein the L-shaped second seal layer comprises a material different from the first seal layer; and

forming a U-shaped high-k dielectric layer in the gate structure.

7. The method of claim 6, wherein after forming the lightly doped drain further comprises:

performing a first etching process to partially remove the first seal layer before forming the lightly doped drain for forming the remaining first seal layer into a first spacer on the sidewall of the gate structure;

forming a second seal layer on the gate structure, the first spacer, and the substrate;

forming a third seal layer on the second seal layer;

performing a second etching process to partially remove the third seal layer for forming a second spacer; and

performing a third etching process to partially remove the second seal layer for forming the L-shaped second seal layer on a sidewall of the first spacer.

8. The method of claim 7, wherein the first seal layer comprises silicon nitride, the second seal layer comprises silicon oxide, and the third seal layer comprises silicon nitride.

9. The method of claim 7, wherein the first etching process comprises an etching back process, the second etching process comprises a dry etching process, and the third etching process comprises a wet etching process.

10. A semiconductor device, comprising:

a substrate;

a gate structure disposed on the substrate, wherein the gate structure comprises a high-k dielectric layer, wherein the high-k dielectric layer is U-shaped;

a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer non-L-shaped; and

a second seal layer disposed on a sidewall of the first seal layer, wherein the second seal layer comprises a material different from the first seal layer and the second seal layer is L-shaped.