Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices

• US 8,519,523 B2
• Filed: 10/03/2011
• Issued: 08/27/2013
• Est. Priority Date: 08/26/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ye, Seng Kim Dalson, Chong, Chin Hui
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/251,980
• Publication Number:
  US 20120018887A1
• Time in Patent Office: 694 Days
• Field of Search: 257/686, 257/723, 257/E25.006, 257/E25.013, 257/E25.021, 257/E25.027, 257/E21.05
• US Class Current: 257/686
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/4382 Applying permanent coating, e.g. in-situ coating
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/043 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 : Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 25/0756 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/10 : the devices having separate containers
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.

Claims

1. A microelectronic package, comprising:

a first substrate having a first external contact at a first surface and a first wire bond contact at a second surface opposite the first surface;

a first microelectronic die electrically connecting with the first substrate;

a second substrate having a second external contact and a second wire bond contact at a third surface facing away from the first substrate;

a second microelectronic die between the first and second substrates, the second microelectronic die being attached to the first microelectronic die;

a first wire connecting the first wire bond contact and a second wire bond contact;

a second wire connecting the second surface of the first substrate to the first microelectronic die;

a third wire connecting the third surface of the second substrate to a central area of the second microelectronic die; and

a molding compound at least partially encapsulating the first and second substrates, the first and second microelectronic dies and the wire without covering the first external contact or the second external contact.

2. The microelectronic package of claim 1 wherein the first substrate is larger than the second substrate.

3. The microelectronic package of claim 1 wherein the first microelectronic die comprises a chip-on-board package construction.

4. The microelectronic package of claim 1 wherein the second microelectronic die comprises a board-on-chip package construction.

5. The microelectronic package of claim 1 with the second substrate having an exposed grid array of electrical contacts to allow for a stacking assembly of two or more package assemblies.

6. The microelectronic package of claim 1 further comprising a mold compound encapsulating the first, second and third sets of wires.

7. The microelectronic package of claim 1 with the first die adjoining the first substrate and with the second die adjoining the second substrate and further comprising a spacer between the first die and the second die.

8. A microelectronic package, comprising:

a first substrate having a first external contact at a first surface and a first wire bond contact at a second surface opposite the first surface;

a first microelectronic die electrically connecting with the first substrate;

a second substrate having a second external contact and a second wire bond contact at a third surface facing away from the first substrate and a fourth surface opposite the third surface, the third surface having a second external contact and a second wire bond contact, wherein the second substrate has a through opening;

a second microelectronic die between the first and second substrates, the second microelectronic die being attached to the first microelectronic die and adjoining the fourth surface;

a wire connecting the first wire bond contact and the second wire bond contact;

a plurality of contacts on the second die to the third surface of the second substrate via the through opening; and

a molding compound at least partially encapsulating the first and second substrates, the first and second microelectronic dies and the wire without covering the first external contact or the second external contact.

9. A stackable multi-electronic die package, comprising:

a first substrate having a first external contact facing a first direction;

a second substrate spaced apart from the first substrate, the second substrate having a second external contact facing a second direction opposite the first direction;

a first microelectronic die and a second microelectronic die between the first and second substrates;

a spacer between the first and second dies;

a first set of wires connecting the second substrate to the first substrate;

a second set of wires connecting the second die to the second substrate via an opening in the second substrate; and

a molding compound at least partially encapsulating the first and second substrates, the first and second dies and the first set of wires without covering the first external contact or the second external contact.

10. The stackable multi-electronic die package of claim 9 further comprising a third set of wires connecting the first die to the first substrate.

11. The stackable multi-electronic die package of claim 9 wherein the first die and first substrate comprise a chip-on-board package construction and the second die and the second substrate comprise a board-on-chip package construction.

12. The stackable multi-electronic die package of claim 9 wherein the first substrate is larger than the second substrate.

13. A method for manufacturing a microelectronic package, comprising:

attaching a first die to a first substrate having a first external contact facing a first direction and a first wire bond contact facing a second direction opposite the first direction;

attaching a second die to the first die;

attaching a second substrate to the second die, the second substrate having a second external contact and a second wire bond contact facing the second direction;

disposing a first wire bond between the first wire bond contact at the first substrate and the second wire bond contact at the second substrate; and

encapsulating the first and second wire bond contacts and the first wire bond with a molding compound without covering the first external contact or the second external contact.

14. The method of claim 13, further comprising:

attaching a first solder ball to the external contact; and

attaching a second solder ball to the second external contact.

15. The method of claim 13 wherein encapsulating the first and second wire bond contacts includes at least partially encapsulating the first and second substrates and the first and second dies with the molding compound.

16. The method of claim 13, further comprising electrically coupling the first die with the first substrate via wirebonding.

17. The method of claim 13 wherein attaching a first die to a first substrate includes attaching the first die to the first substrate in a flip-chip arrangement.

18. The method of claim 13 wherein attaching a first die to a first substrate includes attaching the first die to the first substrate in a chip-on-board arrangement.

19. The method of claim 18, further comprising disposing a second wire bond between a third wire bond contact on the first die and the first wire bond contact at the first substrate and encapsulating the second wire bond with the molding compound.

20. The method of claim 13 wherein attaching a first die to a first substrate includes attaching the first die to the first substrate in a board-on-chip arrangement.

21. The method of claim 13, further comprising providing a spacer between the first die and the second die.

22. The method of claim 13 wherein the first substrate is larger than the second substrate, and wherein disposing a first wire bond includes disposing a first wire bond between the first wire bond contact and the second wire bone contact, the first wire bond contact being located in an area that extends beyond the second substrate.

23. The method of claim 13 wherein the second substrate has a through opening, and wherein the method further comprises extending wires from a plurality of contacts on the second die to the second wire bond contact facing the second direction.

24. The method of claim 13, further comprising testing first and second external contacts, first and second wire bond contacts and first and second dies to determine known good microelectronic packages.