3D semiconductor package interposer with die cavity

• US 8,519,537 B2
• Filed: 06/10/2010
• Issued: 08/27/2013
• Est. Priority Date: 02/26/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jeng, Shin-Puu, Chen, Kim Hong, Hou, Shang-Yun, Shih, Chao-Wen, Yu, Chen-Hua, Hsieh, Cheng-Chieh
• Primary Examiner(s): Williams, Alexander O
• Application Number:
  US12/813,212
• Publication Number:
  US 20110210444A1
• Time in Patent Office: 1,174 Days
• Field of Search: 275/738, 275/737, 275/777, 275/E23.173, 275/E21.509, 275/E23.023, 275/686, 275/685, 275/723, 275/727, 275/728, 275/778, 275/724, 275/668, 275/773, 275/774
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate

Abstract

A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.

Claims

1. A semiconductor device comprising:

a first die;

a second die;

an interposer, the first die being electrically coupled to a first side of the interposer, the second die being electrically coupled to a second side of the interposer; and

a first substrate, the first substrate being electrically coupled at a first side to the second side of the interposer, wherein the substrate includes a cavity extending from the first side partially through the substrate, the second die being positioned within the cavity, and the substrate having at least one through via extending from a first side of the substrate to a second side of the substrate, the substrate configured to be mounted to a second substrate and electrically connecting the at least one via to the second substrate.

2. The semiconductor device of claim 1, further comprising a thermal pad layer along a bottom of the cavity.

3. The semiconductor device of claim 1, wherein the first substrate further comprises a heat conductive layer under the cavity.

4. The semiconductor device of claim 3, wherein the heat conductive layer extends from a surface of the cavity to an opposing side of the first substrate.

5. The semiconductor device of claim 1, wherein the first substrate is electrically coupled to the second side of the interposer using solder bumps having a diameter of 80 μ

m or less.

6. The semiconductor device of claim 5, wherein the solder bumps have a collapsed height of 60 μ

m or less.

7. The semiconductor device of claim 1, wherein the interposer is a silicon interposer.

8. The semiconductor device of claim 1, wherein the first substrate is a laminate substrate.

9. The semiconductor device of claim 1, wherein one of the first die and the second die comprises a logic circuit and the other of the first die and the second die is a memory.

10. A semiconductor device comprising:

an interposer having bond pads on a first side and a second side;

a first die attached to the bond pads on the first side of the interposer by a first plurality of conductive bumps;

a second die attached to the bond pads on the second side of the interposer by a second plurality of conductive bumps; and

a substrate, the substrate being attached at a first side to the bond pads on the second side of the interposer by a third plurality of conductive bumps, the substrate having a cavity extending from the first side partially through the substrate, the second die being positioned within the cavity, wherein a second side of the substrate is planar.

11. The semiconductor device of claim 10, further comprising a thermal gap filler material in the cavity between the second die and the substrate.

12. The semiconductor device of claim 10, wherein the substrate further comprises a heat conductive layer under the cavity.

13. The semiconductor device of claim 12, wherein the heat conductive layer extends from a surface of the cavity to an opposing side of the substrate.

14. The semiconductor device of claim 10, wherein the interposer is a silicon interposer.

15. The semiconductor device of claim 10, wherein the substrate is a laminate substrate.

16. A semiconductor device comprising:

a first die;

a second die;

an interposer, the first die being electrically coupled to a first side of the interposer, the second die being electrically coupled to a second side of the interposer;

a substrate, the substrate being electrically coupled to the second side of the interposer, wherein the substrate includes a cavity extending from a first side of the substrate into the substrate, the second die being positioned within the cavity; and

a heat conductive layer disposed within the cavity and extending from the cavity to a second side of the substrate, a first side of the heat conductive layer substantially level with the second side of the substrate, the second die disposed between the heat conductive layer and the interposer.

17. The device of claim 16, and the substrate having at least one through via extending from the first side to a second side, the substrate configured to be mounted to a target substrate and electrically connecting the at least one via to the target substrate.

18. The device of claim 16, wherein the heat conductive layer comprises a thermal gap filling material.

19. The device of claim 16, wherein the substrate is electrically coupled to the second side of the interposer using solder bumps having a diameter of 80 μ

m or less.