Laser etch via formation

• US 8,519,538 B2
• Filed: 04/28/2010
• Issued: 08/27/2013
• Est. Priority Date: 04/28/2010
• Status: Active Grant

• Current Assignee: Epistar Corporation (Ennostar, Inc.)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsia, Hsing-Kuo, Yu, Chih-Kuang, Chiu, Ching-Hua, Wu, Troy
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US12/768,911
• Publication Number:
  US 20110266674A1
• Time in Patent Office: 1,217 Days
• Field of Search: 257/745, 257/782, 257/774, 257/676, 438/604, 438/629, 438/637, 438/638, 438/640, 438/668, 438/672, 438/675
• US Class Current: 257/745
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/06182 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3171 : the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

The present disclosure provides methods for forming semiconductor devices with laser-etched vias and apparatus including the same. In one embodiment, a method of fabricating a semiconductor device includes providing a substrate having a frontside and a backside, and providing a layer above the frontside of the substrate, the layer having a different composition from the substrate. The method further includes controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate, filling the opening with a conductive material to form a via, removing a portion of the backside of the substrate to expose the via, and electrically coupling a first element to a second element with the via. A semiconductor device fabricated by such a method is also disclosed.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

providing a substrate having a frontside and a backside;

providing a layer above the frontside of the substrate, the layer having a different composition from the substrate and containing a first electrical element;

controlling a laser power and a laser pulse number to laser etch an opening through the layer and at least a portion of the frontside of the substrate;

completely filling the opening with a conductive material to form a via;

forming a passivation layer over the frontside of the substrate, the passivation layer containing electrical interconnection component that electrically couples the first electrical element to the via;

bonding a carrier substrate to the substrate, the passivation layer being disposed between the substrate and the carrier substrate;

removing, after bonding the carrier substrate, a portion of the backside of the substrate to expose the via;

thereafter removing the carrier substrate; and

electrically coupling the first electrical element to a second element on the backside through the via.

2. The method of claim 1, wherein the substrate is comprised of silicon, gallium arsenide (GaAs), gallium nitride (GaN), ceramic, sapphire, a dielectric, or combinations thereof, and wherein the conductive material includes copper, tungsten, aluminum, silver, or combinations thereof.

3. The method of claim 1, wherein the laser etch is performed with the laser power between about 1 milliwatt and about 100 kilowatts.

4. The method of claim 1, wherein the laser etch is performed with the laser pulse number between about 1 and about 300.

5. The method of claim 1, wherein the opening is laser etched without using a resist mask.

6. The method of claim 1, wherein the opening is laser etched to have a diameter ranging between about 40 micron and about 140 micron and a depth ranging between about 10 micron and about 800 micron.

7. The method of claim 1, wherein the opening is laser etched to have an aspect ratio ranging between about 0.25 and about 20.

8. The method of claim 1, wherein the first electrical element is a first semiconductor component of a first die and the second element is a second semiconductor component of a second die.

9. The method of claim 1, further comprising forming a liner layer in the opening, the liner layer comprised of a material selected from TaN, Ta, TiN, Ti, CoW, or combinations thereof.

10. The method of claim 1, further comprising tuning the laser power, a laser frequency, and the laser pulse number to control a taper angle of the opening, and wherein the taper angle is between about 60 degrees and about 90 degrees.

19. The method of claim 8, wherein the substrate and the via are portions of the first die, and wherein the electrically coupling is performed such that the second die is coupled to the first die through the frontside of the substrate.

11. A method of fabricating a semiconductor device, the method comprising:

providing a substrate having a frontside and a backside;

providing a plurality of layers above the frontside of the substrate, the plurality of layers having different compositions from the substrate;

controlling a laser power and a laser pulse number to laser etch an opening through the plurality of layers and at least a portion of the frontside of the substrate, wherein a taper angle of the opening is tuned by the laser power and the laser pulse number;

filling a substantial entirety of the opening with a conductive material to form a via;

bonding a carrier substrate to the frontside of the substrate;

removing, after bonding the carrier substrate, a portion of the backside of the substrate to expose the via;

thereafter removing the carrier substrate; and

electrically coupling a first element to a second element with the via.

12. The method of claim 11, further comprising grinding and polishing a backside of the substrate to expose the via.

13. The method of claim 11, further comprising laser etching a plurality of openings through at least a portion of the substrate, wherein the plurality of openings are etched with different laser power or different laser pulse numbers.

20. The method of claim 11, wherein the electrically coupling is performed such that a first die containing the first element is electrically coupled to a second die containing the second element, wherein the substrate and the via are located on the first die, and wherein the second die is coupled to the first die through the frontside of the substrate.

21. The method of claim 11, wherein the first element is disposed within one of the layers above the frontside of the substrate, and further comprising forming a laterally-extending electrical interconnection component over the frontside of the substrate to electrically couple the via with the first element.

14. A method of fabricating a semiconductor device, the method comprising:

providing a first die having a first surface and a second surface opposite the first surface;

providing a second die having a first surface and a second surface opposite the first surface, the first surface of the second die having contact pads;

laser etching a plurality of openings through the first surface of the first die, each opening of the plurality of openings having an aspect ratio ranging between about 0.25 and about 20;

thereafter completely filling the openings with a conductive material to form a plurality of vias;

bonding a carrier to the first surface of the first die;

polishing, after bonding the carrier, the first die from the second surface until the vias are exposed;

thereafter removing the carrier; and

electrically coupling semiconductor components of the first die to the plurality of vias and to the contact pads of the second die through a first set of redistribution lines.

15. The method of claim 14, wherein each opening of the plurality of openings is formed through layers of different material.

16. The method of claim 14, wherein each opening of the plurality of openings includes a tapered profile having a taper angle between about 60 degrees and about 90 degrees.

17. The method of claim 14, wherein each opening of the plurality of openings has a diameter ranging between about 40 micron and about 140 micron and a depth ranging between about 10 micron and about 800 micron.

18. The method of claim 14, wherein the plurality of vias are comprised of conductive material including copper, tungsten, aluminum, silver, or combinations thereof, and wherein each via of the plurality of vias includes a liner layer, the liner layer comprised of material selected from TaN, Ta, TiN, Ti, CoW, or combinations thereof.