Programming the behavior of individual chips or strata in a 3D stack of integrated circuits

• US 8,519,735 B2
• Filed: 08/25/2011
• Issued: 08/27/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Pang, Liang-Teck, Silberman, Joel A., Wordeman, Matthew R.
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US13/217,734
• Publication Number:
  US 20130049795A1
• Time in Patent Office: 733 Days
• Field of Search: None
• US Class Current: 326/16
• CPC Class Codes: G01R 31/318513 Test of Multi-Chip-Moduls
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

Claims

1. A method for programming strata within a 3D chip stack having two or more strata, the method comprising:

providing a plurality of scannable configuration registers; and

arranging each of the plurality of scannable configuration registers on a respective one of the two or more strata of the 3D chip stack for storing a set of bits,

wherein the set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon.

2. A method for identifying individual stratum within a 3D chip stack having two or more strata and multiple integrated circuits, the method comprising:

providing a plurality of stratum identification circuits, each arranged on a respective one of the two or more strata, and each having N inter-stratum inputs and N inter-stratum outputs, N being an integer equal to or greater than 1, and 2^N being a number of the two or more strata;

interconnecting and driving the inter-stratum inputs from a respective one of the plurality of stratum identification circuits on each of the two or more strata to and by the inter-stratum outputs from a different one of the plurality of stratum identification circuits on an adjacent one of the two or more strata;

providing inter-stratum input signals and inter-stratum output signals as binary encoded values such that the inter-stratum output signals encode a value of the inter-stratum input signals incremented by 1; and

providing the inter-stratum output signals to at least some of the multiple integrated circuits on a same one of the two or more strata stratum so as to provide the encoded value there from as a unique binary pattern on each of the two or more strata.