High-swing differential driver using low-voltage transistors
First Claim
1. A differential line driver having an input node, differential output nodes for coupling to a transmission line with a characteristic impedance Z0, and N driver slices, at least one of the driver slices comprising:
- first and second power nodes for coupling to a power supply;
a first common node;
an impedance device having a resistance and coupled between the first power node and the first common node;
first and second transistors of a first conductivity type, each transistor having a first output terminal coupled to the first common node, a second output terminal, and a control terminal, the control terminals of the first and second transistors coupling to the input node;
a first resistor coupled between the second output terminal of the first transistor and a first one of the differential output nodes;
a second resistor coupled between the second output terminal of the second transistor and a second one of the differential output nodes; and
first and second ESD protectors coupled between at least one of the power nodes and the respective first and second ones of the differential output nodes;
wherein the first and second resistors have substantially the same resistance value, and a sum of the resistances of the impedance device and first resistor is approximately equal to N Z0 ohms, where N is an integer greater than or equal to one.
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Accused Products
Abstract
A differential line driver with N-paralleled slices for driving an impedance-matched transmission line. Each driver slice is a modified H-bridge driver using low-voltage, high-speed transistors. By using a voltage-dropping first resistor in each slice, a high-voltage power supply that would normally damage the transistors can be used to power the driver and produce a differential output signal with peak-to-peak amplitudes that otherwise might not be possible. Each transistor in each driver slice has a resistor disposed between the transistor and the respective output node of the driver to enhance ESD protection of the transistors and, in combination with the first resistor, to impedance match the driver to the transmission line.
96 Citations
29 Claims
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1. A differential line driver having an input node, differential output nodes for coupling to a transmission line with a characteristic impedance Z0, and N driver slices, at least one of the driver slices comprising:
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first and second power nodes for coupling to a power supply; a first common node; an impedance device having a resistance and coupled between the first power node and the first common node; first and second transistors of a first conductivity type, each transistor having a first output terminal coupled to the first common node, a second output terminal, and a control terminal, the control terminals of the first and second transistors coupling to the input node; a first resistor coupled between the second output terminal of the first transistor and a first one of the differential output nodes; a second resistor coupled between the second output terminal of the second transistor and a second one of the differential output nodes; and first and second ESD protectors coupled between at least one of the power nodes and the respective first and second ones of the differential output nodes; wherein the first and second resistors have substantially the same resistance value, and a sum of the resistances of the impedance device and first resistor is approximately equal to N Z0 ohms, where N is an integer greater than or equal to one. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A differential line driver having an input node, differential output nodes for coupling to a transmission line with a characteristic impedance Z0, and N driver slices, the driver slices comprising:
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first and second power nodes, common to all driver slices, for coupling to a power supply; a first node; a first resistor coupled between the first power node and the first node; first and second pMOS transistors, each transistor having a source terminal coupled to the first node, a drain terminal, and a gate terminal, the gate terminals of the first and second transistors coupling to the input node; third and fourth nMOS transistors, each transistor having a source terminal coupled to the second power node, a drain terminal, and a gate terminal, the gate terminals of the third and fourth transistors coupling to the input node; a second resistor coupled between the drain terminal of the first transistor and a first one of the differential output nodes; a third resistor coupled between the drain terminal of the second transistor and a second one of the differential output nodes; a fourth resistor coupled between the drain terminal of the third transistor and a first one of the differential output nodes; and a fifth resistor coupled between the drain terminal of the fourth transistor and a second one of the differential output nodes; first and second ESD protectors coupled between at least one of the power nodes and the respective first and second ones of the differential output nodes; wherein the second and third resistors have substantially the same resistance value and a sum of the resistances of the first resistor and second resistor is approximately equal to N Z0 ohms, and the fourth and fifth resistors each have substantially the same resistance value approximately equal to N Z0 ohms, where N is an integer greater than or equal to one. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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Specification