Method for driving semiconductor device

• US 8,520,426 B2
• Filed: 09/01/2011
• Issued: 08/27/2013
• Est. Priority Date: 09/08/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuki, Tatsuya
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US13/223,499
• Publication Number:
  US 20120057397A1
• Time in Patent Office: 726 Days
• Field of Search: 365/149, 365/104, 365/96, 365/102, 365/72, 365/189.15, 365/189.16, 365/185.14, 365/185.1, 365/185.28, 365/185.15, 365/185.18, 365/191, 365/185.21
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In a driving method of a semiconductor device which conducts a multilevel writing operation, a signal line for controlling on/off of a writing transistor for conducting a writing operation on a memory cell using a transistor including an oxide semiconductor layer is disposed along a bit line, and a multilevel writing operation is conducted with use of, also in a writing operation, a voltage which is applied to a capacitor at a reading operation. The potential of a bit line is detected while data writing is conducted, and thereby whether a potential corresponding to the written data is normally applied to the floating gate can be confirmed without a writing verify operation.

Claims

1. A method for driving a semiconductor device,

the semiconductor device comprising:

a first to m-th memory cells which are connected in series between a source line and a bit line;

a first selection transistor whose gate terminal is electrically connected to a first selection line; and

a second selection transistor whose gate terminal is electrically connected to a second selection line,

wherein each of the first to m-th memory cells comprises;

a first transistor provided on a substrate including a semiconductor material, the first transistor comprising a first source terminal, a first drain terminal, and a first gate terminal electrically connected to a first signal line;

a second transistor including an oxide semiconductor layer, the second transistor comprising a second source terminal, a second drain terminal, and a second gate terminal electrically connected to a second signal line; and

a capacitor of which one terminal is electrically connected to one of m word lines,

wherein the source line is electrically connected to the first source terminal of the m-th memory cell via the second selection transistor,

wherein the bit line is electrically connected to the first drain terminal of the first memory cell via the first selection transistor, and

wherein the second source terminal, the first gate terminal, and the other terminal of the capacitor are electrically connected to one another to form a node,

the method comprising;

detecting a potential of the bit line by supplying potentials to the first selection line and the second selection line to turn on the first selection transistor and the second selection transistor in a writing operation where a potential is supplied to the second signal line to turn on the second transistors, and a potential is supplied to the first signal line to supply a potential to the nodes.

2. The method for driving a semiconductor device, according to claim 1, wherein a potential applied to the first signal line to supply the potential to the node is increased step-by-step.

3. The method for driving a semiconductor device, according to claim 1, wherein the potential in the node is held by turning off the second transistor.

4. The method for driving a semiconductor device, according to claim 1,

wherein in the writing operation, a plurality of different potentials are applied to the in word lines so that a plurality of different potentials are included in the first to m-th memory cells, and

wherein after the second transistors are turned off, supply of potentials to the in word lines is stopped.

5. The method for driving a semiconductor device, according to claim 4, wherein potentials held in the nodes in the first to m-th memory cells after the writing operation is finished include a plurality of different potentials.

6. A method for driving a semiconductor device,

the semiconductor device comprising:

a first to m-th memory cells which are connected in series between a source line and a bit line;

a first selection transistor whose gate terminal is electrically connected to a first selection line; and

a second selection transistor whose gate terminal is electrically connected to a second selection line,

wherein each of the first to m-th memory cells comprises;

a first transistor provided on a substrate including a semiconductor material, the first transistor comprising a first source terminal, a first drain terminal, and a first gate terminal electrically connected to a first signal line;

a second transistor including an oxide semiconductor layer, the second transistor comprising a second source terminal, a second drain terminal, and a second gate terminal electrically connected to a second signal line; and

a capacitor of which one terminal is electrically connected to one of in word lines,

wherein the source line is electrically connected to the first source terminal of the m-th memory cell via the second selection transistor,

wherein the bit line is electrically connected to the first drain terminal of the first memory cell via the first selection transistor, and

wherein the second source terminal, the first gate terminal, and the other terminal of the capacitor are electrically connected to one another to form a node,

the method comprising;

detecting a potential of the bit line by supplying potentials to the first selection line and the second selection line to turn on the first selection transistor and the second selection transistor in a writing operation where a potential is supplied to the second signal line to turn on the second transistors, and a potential is supplied to the first signal line to supply a potential to the nodes; and

after the bit line and the source line are brought into conduction, turning off the second transistors to finish the writing operation.

7. The method for driving a semiconductor device, according to claim 6, wherein a potential applied to the first signal line to supply the potential to the node is increased step-by-step.

8. The method for driving a semiconductor device, according to claim 6, wherein the potential in the node is held by turning off the second transistor.

9. The method for driving a semiconductor device, according to claim 6,

wherein in the writing operation, a plurality of different potentials are applied to the in word lines so that a plurality of different potentials are included in the first to m-th memory cells, and

wherein after the second transistors are turned off, supply of potentials to the in word lines is stopped.

10. The method for driving a semiconductor device, according to claim 9, wherein potentials held in the nodes in the first to m-th memory cells after the writing operation is finished include a plurality of different potentials.

11. A method for driving a semiconductor device,

the semiconductor device comprising:

a first memory cell and a second memory cell which are connected in series between a first line and a second line,

wherein each of the first memory cell and the second memory cell comprises;

a first transistor;

a second transistor, the second transistor includes a semiconductor layer including an oxide semiconductor; and

a capacitor whose first terminal is electrically connected to a gate terminal of the first transistor and a first terminal of the second transistor to form a node,

wherein the first line is electrically connected to a first terminal of the first transistor in the first memory cell,

wherein a second terminal of the first transistor in the first memory cell is electrically connected to a first terminal of the first transistor in the second memory cell, and

wherein the second line is electrically connected to a second terminal of the first transistor in the second memory cell via a third transistor,

the method comprising;

detecting a potential of the first line by turning on the third transistor in a writing operation where the second transistor is turned on, and a potential is supplied to the node.

12. The method for driving a semiconductor device, according to claim 11, wherein the potential supplied to the node is increased step-by-step.

13. The method for driving a semiconductor device, according to claim 11, wherein the potential in the node is held by turning off the second transistor.

14. The method for driving a semiconductor device, according to claim 11,

wherein a second terminal of the capacitor in the first memory cell and a second terminal of the capacitor in the second memory cell are electrically connected to a third line and a fourth line, respectively,

wherein in the writing operation, different potentials are applied to the third line and the fourth line so that different potentials are included in the first memory cell and the second memory cell, and

wherein after the second transistors are turned off, supply of potentials to the third line and the fourth line is stopped.

15. The method for driving a semiconductor device, according to claim 14, wherein potentials held in the nodes in the first memory cell and the second memory cell after the writing operation is finished include different potentials.