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Row address code selection based on locations of substandard memory cells

  • US 8,520,461 B2
  • Filed: 07/08/2010
  • Issued: 08/27/2013
  • Est. Priority Date: 09/18/2009
  • Status: Active Grant
First Claim
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1. A method of operating a memory device, comprising:

  • identifying a first plurality of memory blocks each comprising at least one substandard memory cell;

    identifying a second plurality of memory blocks each comprising no substandard memory cells;

    generating a plurality of candidate first row address codes by omitting different one or more bits of a row address corresponding to two or more memory blocks, where at least one of the two or more memory blocks is from the first plurality of memory blocks;

    selecting one of the plurality of candidate first row address codes as a first row address code;

    generating a second row address code by omitting one or more bits of a row address corresponding to at least two memory blocks from the second plurality of memory blocks;

    performing a first refresh operation simultaneously on the memory blocks having the first row address code value using a first refresh period; and

    performing a second refresh operation simultaneously on the memory blocks having the second row address code value with a second refresh period longer than the first refresh period.

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