Row address code selection based on locations of substandard memory cells
First Claim
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1. A method of operating a memory device, comprising:
- identifying a first plurality of memory blocks each comprising at least one substandard memory cell;
identifying a second plurality of memory blocks each comprising no substandard memory cells;
generating a plurality of candidate first row address codes by omitting different one or more bits of a row address corresponding to two or more memory blocks, where at least one of the two or more memory blocks is from the first plurality of memory blocks;
selecting one of the plurality of candidate first row address codes as a first row address code;
generating a second row address code by omitting one or more bits of a row address corresponding to at least two memory blocks from the second plurality of memory blocks;
performing a first refresh operation simultaneously on the memory blocks having the first row address code value using a first refresh period; and
performing a second refresh operation simultaneously on the memory blocks having the second row address code value with a second refresh period longer than the first refresh period.
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Abstract
A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together.
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Citations
20 Claims
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1. A method of operating a memory device, comprising:
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identifying a first plurality of memory blocks each comprising at least one substandard memory cell; identifying a second plurality of memory blocks each comprising no substandard memory cells; generating a plurality of candidate first row address codes by omitting different one or more bits of a row address corresponding to two or more memory blocks, where at least one of the two or more memory blocks is from the first plurality of memory blocks; selecting one of the plurality of candidate first row address codes as a first row address code; generating a second row address code by omitting one or more bits of a row address corresponding to at least two memory blocks from the second plurality of memory blocks; performing a first refresh operation simultaneously on the memory blocks having the first row address code value using a first refresh period; and performing a second refresh operation simultaneously on the memory blocks having the second row address code value with a second refresh period longer than the first refresh period. - View Dependent Claims (2, 3, 4, 8, 9)
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5. A method of operating a memory device, comprising:
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identifying a first plurality of memory blocks each comprising at least one substandard memory cell; identifying a second plurality of memory blocks each comprising no substandard memory cells; generating a first row address code by omitting one or more bits of a row address corresponding to two or more memory blocks, where at least one of the two or more memory blocks is from the first plurality of memory blocks; generating a second row address code by omitting one or more bits of a row address corresponding to at least two memory blocks from the second plurality of memory blocks; performing a first refresh operation simultaneously on the memory blocks having the first row address code value using a first refresh period; and performing a second refresh operation simultaneously on the memory blocks having the second row address code value with a second refresh period longer than the first refresh period, wherein generating the first row address code comprises; identifying a plurality of unabbreviated row address code values each having a bit-length “
N” and
corresponding to a single memory block;identifying a plurality of abbreviated row address code values each having a bit-length less than “
N” and
corresponding to more than one of the unabbreviated row address code values and the corresponding memory blocks; anddistinguishing one of the abbreviated row address code values as the first value upon determining that the one of the abbreviated row address code values corresponds to at least one memory block comprising a substandard memory cell. - View Dependent Claims (6, 7)
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10. A method of operating a memory device, comprising:
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identifying a row address code corresponding to a plurality of memory blocks, wherein different values of the row address code identify different ones of the plurality of memory blocks; determining whether each of the plurality of memory blocks comprises at least one substandard memory cell; generating a plurality of candidate abbreviated row address codes by omitting different one or more bits of the row address code based on which of the memory blocks comprises at least one substandard memory cell; selecting one of the plurality of candidate abbreviated row address codes as an abbreviated row address code; and performing a refresh operation by simultaneously refreshing memory blocks having the same value of the abbreviated row address code. - View Dependent Claims (11, 12, 13, 14)
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15. A method of performing a refresh operation in a memory device, comprising:
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refreshing a first group of memory blocks using a first refresh period; and
refreshing a second group of memory blocks using a second refresh period longer than the first refresh period;wherein the first group comprises memory blocks with substandard memory cells and the second group comprises no memory blocks with substandard memory cells; selecting an abbreviated row address code from a plurality of candidate abbreviated row address codes; and wherein the grouping of the memory blocks into the first and second groups minimizes the total number of memory blocks using the first refresh period while allowing memory cells with the same value of the abbreviated row address code to be refreshed simultaneously. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification