RF bus controller

• US 8,520,657 B2
• Filed: 12/26/2011
• Issued: 08/27/2013
• Est. Priority Date: 01/31/2007
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza (Reza)
• Primary Examiner(s): Wu, Jianye
• Application Number:
  US13/337,243
• Publication Number:
  US 20120093132A1
• Time in Patent Office: 610 Days
• Field of Search: None
• US Class Current: 370/344
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/1903 including wave guides
• CPC Class Codes: H04L 12/40013 Details regarding a bus controller
• CPC Class Codes: H04L 12/40143 involving priority mechanisms hybrid switching fabrics H04L12/6402; intermediate storage or scheduling H04L49/90; time-division multiplex systems H04J3/00
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/417 with deterministic access, e.g. token passing
• CPC Class Codes: H04W 72/04 Wireless resource allocation
• CPC Class Codes: H04W 74/00 Wireless channel access

Abstract

A radio frequency (RF) bus controller includes an interface and a processing module. The interface is coupled for communicating intra-device RF bus access requests and allocations. The processing module is coupled to receive an access request to an RF bus via the interface; determine RF bus resource availability; and when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource in response to the access request.

Claims

1. A radio frequency (RF) bus controller comprises:

a wireless interface operable to communicate with a plurality of integrated circuits (ICs) coupled to a supporting substrate, in a 60 GHz frequency band; and

a processing module, coupled to the wireless interface, the processing module operable to;

receive an access request to access an RF bus via the wireless interface from an IC of the plurality of ICs, wherein the RF bus provides communication between the plurality of ICs in the 60 GHz frequency band;

determine RF bus resource availability; and

when sufficient RF bus resources are available to fulfill the access request, allocate, via the interface, at least one RF bus resource to the IC in response to the access request.

2. The RF bus controller of claim 1, wherein the receiving the access request comprises at least one of:

receiving the access request in response to a polling request;

receiving the access request in an allocated time division multiple access (TDMA) slot;

receiving the access request in response to a token ring passing scheme;

receiving the access request in accordance with a carrier sense multiple access (CSMA) protocol of a RF bus control resource;

receiving the access request in accordance with an interrupt protocol;

receiving the access request in an allocated frequency division multiple access (FDMA) slot; and

receiving the access request in an allocated code division multiple access (CDMA) slot.

3. The RF bus controller of claim 1, wherein the determining the RF bus resource availability comprises:

determining at least one of;

transmission requirements of the access request, RF bus capabilities of requestor, and RF bus capabilities of target;

determining required RF bus resources based on the at least one of the transmission requirements, the RF bus capabilities of the requestor, and the RF bus capabilities of the target; and

determining whether the required RF bus resources are available for allocation.

4. The RF bus controller of claim 3, wherein the determining the transmission requirements of the access request comprises at least one of:

determining amount of information to be conveyed;

determining priority level of requestor;

determining priority level of the information to be conveyed;

determining real-time or non-real-time aspect of the information to be conveyed; and

determining information conveyance integrity requirements.

5. The RF bus controller of claim 4, wherein the determining the information conveyance integrity requirements comprises at least one of:

determining level of rate encoding;

determining level of interleaving;

determining level of error correction; and

determining level of acknowledgement.

6. The RF bus controller of claim 3, wherein the determining the RF bus resource availability further comprises:

identifying a type of RF bus resource, wherein types of RF bus resources include one or more of;

single channel Single Input Single Output (SISO), single channel Multiple Input Multiple Output (MIMO), multiple channel SISO, multiple channel MIMO, null-reinforce multipath patterning, frequency band selection, waveguide RF path, free space RF path, free space RF path, time division multiple access (TDMA) time slot, frequency division multiple access (FDMA) frequency slot, code division multiple access (CDMA) code slot, proprietary resource, and carrier sense multiple access (CSMA).

7. The RF bus controller of claim 3, when the processing module further functions to:

when the sufficient RF bus resources are not available to fulfill the access request, determining available RF bus resources;

determining whether the access request can be accommodated by the available RF bus resources;

when the access request can be accommodated by the available RF bus resources, allocating the available RF bus resources to for the access request;

when the access request cannot be accommodated by the available RF bus resources, queuing the access request.

8. The RF bus controller of claim 3, when the processing module further functions to:

when the sufficient RF bus resources are not available to fulfill the access request, determining whether priority of requestor is at or above a first priority level;

when priority of the requestor is at or above the first priority level, determining whether allocated RF bus resources can be reallocated to make available the sufficient RF bus resources;

when the RF bus resources can be reallocated, reallocating at least some of the allocated RF bus resources;

when the allocated RF bus resources cannot be reallocated, determining whether the priority of the requestor is of a second priority level;

when the priority level of the requestor is of the second priority level, reclaiming RF bus resources from the allocated RF bus resources to provide the sufficient RF bus resources; and

when the priority level of the requestor is below the second priority level, queuing the access request.

9. The RF bus controller of claim 8, wherein the allocating of the at least one RF bus resource comprises:

allocating at least one of;

single channel Single Input Single Output (SISO), single channel Multiple Input Multiple Output (MIMO), multiple channel SISO, multiple channel MIMO, null-reinforce multipath patterning, frequency band selection, waveguide RF path, free space RF path, free space RF path, time division multiple access (TDMA) time slot, frequency division multiple access (FDMA) frequency slot, code division multiple access (CDMA) code slot, and a proprietary resource.

10. The RF bus controller of claim 1, wherein the wireless interface comprises at least one of:

first processing module to access a control RF communication path having a different frequency than a frequency of the RF bus;

second processing module to access a control time slot of a time division multiple access partitioning of the RF bus;

third processing module to access a control frequency slot of a frequency division multiple access partitioning of the RF bus; and

fourth processing module to access the RF bus for communicating the intra-device RF bus access requests and allocations via a carrier sense multiple access (CSMA) protocol.

11. A radio frequency (RF) bus controller comprises:

an interface for communicating RF bus access information in a 60 GHz frequency band; and

a processing module coupled to the interface, the processing module operable to;

determine access requirements to an RF bus for one of a plurality of circuit modules of an integrated circuit (IC) on a printed circuit board (PCB), wherein the PCB includes a plurality of integrated circuits, wherein the RF bus communicates in the 60 GHz frequency band;

determine RF bus resource availability;

in accordance with at least one of;

inter-IC communication to another integrated circuit of the plurality of integrated circuits on the PCB, and intra-IC communication to another one of the plurality of circuit modules on the IC; and

allocate, via the interface, RF bus resources in accordance with the access requirements and the RF bus resource availability.

12. The RF bus controller of claim 11, wherein the processing module is further operable to:

determine whether the access requirements pertain to at least one of;

the inter-IC communication and the intra-IC communication.

13. The RF bus controller of claim 12 wherein the processing module determines RF bus resource availability in accordance with inter-IC communication and the intra-IC communication.

14. The RF bus controller of claim 11, wherein the determining access requirements comprises at least one of:

determining system configuration;

determining system level RF bus resources;

determining application level RF bus resources;

determining RF bus capabilities of requestor;

determining RF bus capabilities of target;

determining amount of information to be conveyed;

determining priority level of requestor;

determining priority level of the information to be conveyed;

determining real-time or non-real-time aspect of the information to be conveyed; and

determining information conveyance integrity requirements.

15. The RF bus controller of claim 14, wherein the system configuration comprises at least one of:

inter-IC RF data bus, inter-IC RF instruction bus, inter-IC RF control bus, intra-IC RF data bus, intra-IC RF instruction bus, intra-IC RF control bus, number of integrated circuits (ICs) in the system, types of ICs in the device, and bus interface capabilities of the ICs.

16. The RF bus controller of claim 14, wherein the determining the information conveyance integrity requirements comprises at least one of:

determining level of rate encoding;

determining level of interleaving;

determining level of error correction; and

determining level of acknowledgement.

17. The RF bus controller of claim 14, wherein each of the system level RF bus resources and the application level RF bus resources comprises at least one of:

single channel Single Input Single Output (SISO), single channel Multiple Input Multiple Output (MIMO), multiple channel SISO, multiple channel MIMO, null-reinforce multipath patterning, frequency band selection, waveguide RF path, free space RF path, free space RF path, time division multiple access (TDMA) time slot, frequency division multiple access (FDMA) frequency slot, code division multiple access (CDMA) code slot, proprietary resource, and carrier sense multiple access (CSMA).

18. The RF bus controller of claim 11, wherein the allocating the RF bus resources in accordance with the access requirements and the RF bus resource availability comprises:

determining whether sufficient RF bus resources are available to fulfill the access requirements;

when the sufficient RF bus resources are available to fulfill the access request, allocating the sufficient RF bus resources to a requestor;

when the sufficient RF bus resources are not available to fulfill the access request, determining available RF bus resources;

determining whether the access requirements can be accommodated by the available RF bus resources;

when the access request can be accommodated by the available RF bus resources, allocating the available RF bus resources to the requestor;

when the access request cannot be accommodated by the available RF bus resources, queuing the access requirements.

19. The RF bus controller of claim 11, wherein the interface comprises at least one of:

first processing module to access a control RF communication path having a different frequency than a frequency of the RF bus;

second processing module to access a control time slot of a time division multiple access partitioning of the RF bus;

third processing module to access a control frequency slot of a frequency division multiple access partitioning of the RF bus; and

fourth processing module to access the RF bus for communicating the intra-device RF bus access requests and allocations via a carrier sense multiple access (CSMA) protocol.

20. The RF bus controller of claim 11, wherein the RF bus includes one or more of:

a free-space RF communication path, a waveguide RF communication path, and a dielectric RF communication path.