Method of using a calibration system to generate a latency value

• US 8,521,439 B2
• Filed: 05/10/2010
• Issued: 08/27/2013
• Est. Priority Date: 05/08/2009
• Status: Expired due to Fees

• Current Assignee: Allergan, Inc. (Canada) (Abbvie Incorporated), Allergan Industrie SAS (Abbvie Incorporated), Pulsar Informatics, Inc.
• Original Assignee: Pulsar Informatics, Inc.
• Inventors: Mott, Christopher Grey, Mollicone, Daniel Joseph
• Primary Examiner(s): Whaley, Pablo S
• Application Number:
  US12/777,107
• Publication Number:
  US 20100312508A1
• Time in Patent Office: 1,205 Days
• Field of Search: None
• US Class Current: 702/19
• CPC Class Codes: G16H 40/63 for local operation

Abstract

Methods are provided for calibrating stimulus-response test systems which include a stimulus output device for delivering a stimulus to a subject; and a response input device for receiving a response from the subject. One such method comprises: sensing the stimulus event output by the stimulus output device; recording a calibrator stimulus time associated with detection of the stimulus event in a calibrator separate from the stimulus-response test system; generating a calibrator response after sensing the stimulus event, the calibrator response causing a response input port of the stimulus-response test system to receive a calibrator response signal and to deliver a corresponding calibrator response signal to the test controller; recording a calibrator response time associated with generation of the calibrator response in the calibrator; and determining a latency value associated with the stimulus-response test system based at least in part on a difference between the calibrator response time and the calibrator stimulus time.

Claims

1. A method of using a calibration system to generate a latency estimate for calibrating a stimulus-response test system, wherein the method comprises:

[a] providing a calibration system comprising a stimulus sensor, a response actuator device, and a first set of one or more processors;

[b] providing a stimulus-response test system comprising a stimulus output device for delivering stimuli to a subject, a response input device for receiving responses to the stimuli, a second set of one or more processors, and a response input interface for interfacing between the response input device and the second set of processors;

[c] sensing, using the stimulus sensor, a stimulus output event, the stimulus output event being indicative of delivery of stimulus by the stimulus output device to a subject;

[d] recording, using one or more of the first and second set of processors, a stimulus time associated with sensing the stimulus output event;

[e] generating, by one or more of the first and second set of processors, a calibrator response after sensing the stimulus output event, wherein generating the calibrator response comprises;

sending a response actuation signal from the first set of processors to the response actuator device, thereby

causing the response actuator device to physically actuate the response input device via mechanical action, and thereby

causing the response input device to provide a response input signal to the response input interface;

[f] recording, using one or more of the first and second set of processors, a response time associated with generating the calibrator response;

[g] determining, using one or more of the first and second set of processors, a calibrator delay (t_stim/tresp) based on a difference between the stimulus and response times;

[h] receiving a test system delay (t_tot) at one or more of the first and second set of processors, the test system delay representing a time difference between generating the stimulus at the test system and recording the response at the test system; and

[i] determining, using one or more of the first and second set of processors, a latency value (t_lat) based on a difference between the test system delay (t_tot) and the calibrator delay (t_stim/resp).

2. A method according to claim 1 further comprising:

recording a test-system stimulus time, the test-system stimulus time being associated with when at least one of the second set of processors outputs a signal causing the stimulus output device to deliver stimulus; and

recording a test-system response time, the test-system response time being associated with when at least one of the second set of processors receives the response input signal from the response input interface;

wherein receiving the test system delay t_tot comprises determining a difference between the test-system response time and the test-system stimulus time.

3. A method according to claim 1 comprising:

[j] delaying for a delay period after sensing the stimulus output event in step [c] but before generating the calibrator response in step [e].

4. A method according to claim 1 further comprising:

[k] determining a plurality of latency values t_lat by repeating steps [c] through [i] a plurality of times such that for each repetition of steps [c] through [i] a corresponding latency value t_lat is determined; and

[l] determining a statistically expected latency value E[t_lat] based at least in part on the determined plurality of latency values t_lat.

5. A method according to claim 3 further comprising:

[k] determining a plurality of latency values t_lat by repeating steps [c] through [j] a plurality of times such that for each repetition of steps [c] through [j] a corresponding latency value t_lat is determined; and

[l] determining a statistically expected latency value E[t_lat] based at least in part on the determined plurality of latency values t_lat.

6. A method according to claim 5 wherein delaying for the delay period after sensing the stimulus output event but before generating the calibrator response comprises at least one of:

delaying for a constant delay period in each repetition of steps [c] through [j];

delaying for a random delay period from a probability distribution in each repetition of steps [c] through [j];

delaying for a sequentially increasing delay period in each sequential repetition of steps [c] through [j]; and

delaying for a sequentially decreasing delay period in each sequential repetition of steps [c] through [j].

7. A method according to claim 4 further comprising:

[m] determining a parameter indicative of the variability of the determined plurality of latency values t_lat.

8. A method according to claim 7 wherein the determined parameter indicative of the variability of the determined plurality of latency values t_lat is based at least in part on a standard deviation of the determined plurality of latency values t_lat.

9. A method according to claim 7 wherein the determined parameter indicative of the variability of the determined plurality of latency values t_lat is based at least in part on the range of the plurality of latency values t_lat, where the range is determined by a difference between a maximum and a minimum of the plurality of latency values t_lat.

10. A method according to claim 4 further comprising:

[k] communicating the statistically expected latency value E[t_lat] to at least one processor of the second set of processors.

11. A method of using a calibration system to calibrate a stimulus-response test system, wherein the method comprises:

[a] providing a calibration system comprising a stimulus sensor, a response actuator device, and a first set of one or more processors;

[b] providing a stimulus-response test system comprising a stimulus output device for delivering stimuli to a subject, a response input device for receiving responses to the stimuli, a second set of one or more processors, and a response input interface for interfacing between the response input device and the second set of processors;

[c] sensing, using the stimulus sensor, a stimulus output event, the stimulus output event being indicative of delivery of stimulus by the stimulus output device to a subject;

[d] recording, using one or more of the first and second set of processors, a stimulus time associated with sensing the stimulus output event;

[e] generating, by one or more of the first and second set of processors, a calibrator response after sensing the stimulus output event, wherein generating the calibrator response comprises;

sending a response actuation signal from the first set of processors to the response actuator device, thereby

causing the response actuator device to physically actuate the response input device via mechanical action, and thereby

causing the response input device to provide a response input signal to the response input interface;

[f] recording, using one or more of the first and second set of processors, a response time associated with generating the calibrator response;

[g] determining, using one or more of the first and second set of processors, a calibrator delay (t_stim/tresp) based on a difference between the stimulus and response times;

[h] receiving a test system delay (t_tot) at one or more of the first and second set of processors, the test system delay representing a time difference between generating the stimulus at the test system and recording the response at the test system;

[i] determining, using one or more of the first and second set of processors, a latency value (t_lat) based on a difference between the test system delay (t_tot) and the calibrator delay (t_stim/resp); and

[j] using the latency value (t_lat) to calibrate one or more response times detected by the stimulus-response test system.

12. A method according to claim 11 wherein using the latency value (t_lat) to calibrate one or more response times detected by the stimulus-response test system comprises subtracting the latency value (t_lat) from at least one of the one or more response times.