System and apparatus for flash memory data management

• US 8,521,971 B2
• Filed: 04/10/2012
• Issued: 08/27/2013
• Est. Priority Date: 11/20/2006
• Status: Active Grant

• Current Assignee: Silicon Motion
• Original Assignee: Silicon Motion
• Inventors: Lee, Chun-Kun, Hsiao, Wei-Yi
• Primary Examiner(s): Elmore, Reba I
• Application Number:
  US13/443,342
• Publication Number:
  US 20120198142A1
• Time in Patent Office: 504 Days
• Field of Search: 711/103, 711/156
• US Class Current: 711/156
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0628 making use of a particular technique
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

The system and apparatus for managing flash memory data includes a host transmitting data, wherein when the data transmitted from the host have a first time transmission trait and the address for the data indicates a temporary address, temporary data are retrieved from the temporary address to an external buffer. A writing command is then executed and the temporary data having a destination address are written to a flash memory buffer. When the flash memory buffer is not full, the buffer data are written into a temporary block of the flash memory. The writing of buffer data into the temporary block includes using an address changing command, or executing a writing command to rewrite the external buffer data to the flash memory buffer so that the data are written into the temporary block.

Claims

1. An apparatus for managing flash memory data, comprising:

a flash memory including a flash memory buffer, a destination block, and a temporary block; and

a controller, external to the flash memory, comprising an external buffer;

wherein the controller is configured to receive a write command and data having a destination address corresponding to the destination block, store the data in the external buffer, and, responsive to the write command, transmit the data in the external buffer to the flash memory buffer; and

wherein the controller is further configured to determine if a data length of the data is not less than a page size of a page of the destination block and, if the data length of the data is less than the page size of the page of the destination block, the controller is configured to cause the data to be written to the temporary block.

2. The apparatus of claim 1, wherein the controller is configured to receive the write command and the data having a destination address from a host external to the apparatus.

3. The apparatus of claim 1, wherein the data is written to the temporary block responsive to assignment of a temporary address, within the flash memory buffer, to the data by the controller.

4. The apparatus of claim 1, wherein when the flash memory buffer is full, the controller is configured to cause the data to be written to the destination block in accordance with the destination address.

5. The apparatus of claim 2, wherein the controller is configured to determine whether storage of data from the host in the external buffer has stopped and the controller is further configured to determine if the flash memory buffer is full responsive to the determination that storage of data from the host to the external buffer has stopped.

6. The apparatus of claim 2, wherein the controller is configured to determine whether storage of data from the host in the external buffer has stopped while the data is still being stored in the external buffer, determine whether the flash memory buffer is full, and cause the data to be written to the temporary block if the flash memory buffer is not full.

7. The apparatus of claim 6, wherein when the data are still being stored in the external buffer and the flash memory buffer is full, the controller is configured to cause the data to be written into the destination block within the flash memory according to the destination address, and when the data are completely written to the destination block, the flash memory is configured to execute a write command and accumulate the destination address.

8. A method for managing flash memory data to be stored in a memory device, wherein the memory device comprises a flash memory including a flash memory buffer, a destination block, and a temporary block, and a controller, external to the flash memory, comprising an external buffer, the method comprising:

receiving a write command and data having a destination address corresponding to the destination block by the controller;

storing the data in the external buffer by the controller; and

responsive to the write command, transmitting the data in the external buffer to the flash memory buffer by the controller;

wherein the controller is further configured to determine if a data length of the data is not less than a page size of a page of the destination block and, if the data length of the data is less than the page size of the page of the destination block, the controller is configured to cause the data to be written to the temporary block.

9. The method of claim 8, wherein the controller is configured to receive the write command and the data having a destination address from a host external to the memory device.

10. The method of claim 8, wherein the data is written to the temporary block responsive to assignment of a temporary address, within the flash memory buffer, to the data by the controller.