Information processing apparatus and access control method

• US 8,521,977 B2
• Filed: 10/17/2012
• Issued: 08/27/2013
• Est. Priority Date: 12/28/2011
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ueki, Toshikazu, Okada, Seishi, Koinuma, Hideyuki, Sugizaki, Go
• Primary Examiner(s): NGUYEN, HIEP T
• Application Number:
  US13/654,274
• Publication Number:
  US 20130173867A1
• Time in Patent Office: 314 Days
• Field of Search: None
• US Class Current: 711/163
• CPC Class Codes: G06F 11/2033 switching over of hardware resources
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering

Abstract

An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Claims

1. An information processing apparatus comprising:

a first node that includes a first storing unit configured to store first identification information; and

a second node that includes a second storing unit configured to store second identification information and includes a shared memory, the second node being coupled with the first node via an interconnect, wherein

the first node includes a first processor including a transmitting unit that transmits a request for requesting an access to the shared memory, by attaching address information of the shared memory and the first identification information, and

the second node includes a determining unit that determines whether or not an access to the shared memory is permitted based on the second identification information and the first identification information that is included in the request transmitted from the first node,

the first processor further includes a cache memory that retains data obtained from the shared memory, and

the first processor writes the data retained by the cache memory back to the shared memory in the second node when the determining unit in the second node rejects an access of the request for transferring data from the shared memory to the cache memory.

2. The information processing apparatus according to claim 1, wherein

the second node further includes a second processor that notifies identification information corresponding to the second identification information to the first node, and

the first processor stores the identification information notified from the second processor to the first storing unit.

3. The information processing apparatus according to claim 2, further comprising a third node that includes a third processor, wherein

the second processor further executes:

updating the second identification information when an error corresponding to the first node is detected;

notifying identification information corresponding to the updated second identification information to the third processor that accesses the shared memory; and

the determining unit does not permit an access of the request transmitted from the first node when the first identification information included in the request does not correspond to the second identification information.

4. The information processing apparatus according to claim 1, wherein

the determining unit permits an access of the request for writing back the data retained by the cache memory included in the first processor in the first node to the shared memory in the second node without a determination based on the second identification information and the first identification information included in the request.

5. The information processing apparatus according to claim 4, wherein

the request further includes third identification information that indicates access type of the request;

and

the determining unit permits an access of the request without a determination based on the first identification information and the second identification information when the third identification information included in the request transmitted from the first node indicates writing back the data retained by the cache memory to the shared memory.

6. The information processing apparatus according to claim 1, wherein

the shared memory includes a plurality of segments each having a predetermined size;

the second storing unit stores a plurality of pieces of the second identification information each of which corresponds to one of the plurality of the segments included in the shared memory; and

the determining unit determines whether or not an access to the shared memory is permitted based on the first identification information and the second identification information corresponding to the address information included in the request.

7. The information processing apparatus according to claim 6, wherein

the plurality of segments included in the shared memory includes:

a protect area with which an access protection based on the first identification information and the second identification information is performed by the determining unit; and

a non-protect area with which the access protection is not performed, and

the determining unit determines whether or not an access to the protect area of the shared memory is permitted based on the second identification information corresponding to the protect area and the first identification information that is included in the request transmitted from the first node.

8. The information processing apparatus according to claim 7, wherein

the second processor stores specific identification information, as the second identification information corresponding to the non-protect area, to the second storing unit, and

the determining unit permits the access of the request for accessing the non-protect area from the first node without a determination based on the first identification information and the second identification information when the second identification information corresponding to the segment to which the request accesses is the specific identification information.

9. An access control method executed by an information processing apparatus including a first node and a second node, the first node including a first processor, the second node being coupled with the first node via an interconnect and including a shared memory and a determining unit configured to determine an access permission to the shared memory, the access control method comprising:

transmitting, using the first processor, a request for requesting an access to the shared memory, by attaching address information of the shared memory and first identification information;

determining, using the determining unit, whether or not an access to the shared memory is permitted based on second identification information and the first identification information that is included in the request transmitted from the first node, the second identification information corresponding to the shared memory and being set in advance; and

writing, using the first processor that includes a cache memory retaining data obtained from the shared memory, the data retained by the cache memory back to the shared memory in the second node when the determining unit in the second node rejects an access of the request for transferring data from the shared memory to the cache memory.

10. The access control method according to claim 9, further comprising:

notifying, using a second processor included in the second node, identification information corresponding to the set second identification information to the first node, and

utilizing, using the first processor, the identification information notified from the second processor as the first identification information.

11. The access control method according to claim 9, further comprising:

updating, using a second processor included in the second node, the second identification information when an error corresponding to the first node is detected;

notifying, using the second processor, identification information corresponding to the updated second identification information to a third processor included in a third node, the third processor accessing the shared memory; and

rejecting, using the determining unit, an access of the request transmitted from the first node when the first identification information included in the request does not correspond to the second identification information.

12. The access control method according to claim 9, further comprising:

permitting, using the determining unit, an access of the request for writing back the data retained by the cache memory included in the first processor in the first node to the shared memory in the second node without a determination based on the second identification information and the first identification information included in the request.

13. The access control method according to claim 12, further comprising

permitting, using the determining unit, an access of the request without a determination based on the first identification information and the second identification information when third identification information included in the request transmitted from the first node indicates writing back the data retained by the cache memory to the shared memory.

14. The access control method according to claim 9, further comprising:

setting, using the second processor, a plurality of pieces of the second identification information each of which corresponds to one of a plurality of segments included in the shared memory;

determining, using the determining unit, whether or not an access to the shared memory is permitted based on the first identification information and the second identification information corresponding to the address information included in the request.

15. The access control method according to claim 14, further comprising:

setting, using the second processor, a protect area for one of the segments and a non-protect area for another one of the segments, the protect area being an area with which an access protection based on the first identification information and the second identification information is performed by the determining unit, the non-protect area being an area with which the access protection is not performed; and

determining, using the determining unit, whether or not an access to the protect area of the shared memory is permitted based on the second identification information corresponding to the protect area and the first identification information that is included in the request transmitted from the first node.

16. The access control method according to claim 15, wherein

setting, using the second processor, specific identification information as the second identification information corresponding to the non-protect area;

and

permitting, using the determining unit, the access of the request for accessing the non-protect area from the first node without a determination based on the first identification information and the second identification information when the second identification information corresponding to the segment to which the request accesses is the specific identification information.