Providing silicon integrated code for a system

• US 8,522,066 B2
• Filed: 06/25/2010
• Issued: 08/27/2013
• Est. Priority Date: 06/25/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zimmer, Vincent J., Xing, Bin, Robinson, Scott H.
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Hicks, Austin
• Application Number:
  US12/823,343
• Publication Number:
  US 20110320798A1
• Time in Patent Office: 1,159 Days
• Field of Search: 713/1, 713/2, 713/100
• US Class Current: 713/503
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 21/14 against software analysis or reverse engineering, e.g. by obfuscation
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 21/575 Secure boot
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed.

Claims

1. An apparatus comprising:

a non-volatile storage to store semiconductor integrated code (SIC) corresponding to platform independent code of a processor manufacturer, the SIC including an embedded processor logic to initialize a processor and at least one communication link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to pre-boot code of an original equipment manufacturer (OEM), wherein the SIC is provided as a binary to the OEM for inclusion in the non-volatile storage, the non-volatile storage including OEM basic input/output system (BIOS), wherein responsive to a system restart, a firmware integration table (FIT) is to be accessed to determine whether a SIC entry in the FIT corresponds to a maximum revision of the SIC, an initial program loader (IPL) is to be executed, the SIC is to be executed if the IPL is executed successfully to initialize the processor, wherein a boot failure is to occur responsive to at least one of the FIT is not able to be accessed, the SIC entry does not correspond to the maximum revision, the SIC is non-authenticated, and the processor is not properly initialized.

2. The apparatus of claim 1, further comprising an initial program loader (IPL) to load the SIC, the IPL to be launched from microcode of the processor, wherein the IPL is to authenticate the SIC and then to launch the SIC.

3. The apparatus of claim 2, wherein the IPL is to access a firmware interface table (FIT) having an entry including a pointer to point to a location of the SIC.

4. The apparatus of claim 1, wherein the nonvolatile storage includes a plurality of SIC revisions, each associated with a corresponding SIC data module, and wherein the IPL is to select one of the plurality of SIC versions and SIC data modules to launch based on entries in the FIT.

5. The apparatus of claim 4, wherein the SIC data module includes processor manufacturer data, OEM data, and end user data, wherein the OEM data and the end user data is platform dependent.

6. The apparatus of claim 5, wherein the OEM data is trusted data that is signed by the processor manufacturer prior to insertion into the non-volatile storage.

7. The apparatus of claim 1, wherein the non-volatile storage is of a processor package including a plurality of cores, at least one microcode store, and an integrated memory controller.

8. The apparatus of claim 1, wherein the SIC is to sequester a portion of the memory for the processor, wherein the sequestered portion is to be invisible to an operating system.

9. The apparatus of claim 1, wherein the processor is to store a binary translator in the sequestered portion.

10. A method comprising:

receiving, via a hot plug indicia, an indication in a system during runtime operations that at least one new component is to be dynamically incorporated into the system;

triggering a power management operation via operating system power management (OSPM) code that executes on a processor of the system responsive to the indication;

invoking transitory semiconductor integrated code (SIC) from the OSPM code to execute on the processor and without entry into a system management mode, the transitory SIC corresponding to platform independent code of a processor manufacturer, and executing initialization of the at least one component using the transitory SIC, based on one or more entries of a firmware integration table (FIT) and input from the OSPM code; and

unloading the transitory SIC and returning to the OSPM code, wherein the transitory SIC is provided as a binary module by the processor manufacturer to an original equipment manufacturer (OEM) of the system.

11. The method of claim 10, further comprising accessing a SIC data module using the SIC, based on an entry in the firmware integration table (FIT).

12. The method of claim 11, further comprising executing the initialization using information in the SIC data module.

13. The method of claim 10, further comprising launching the SIC to perform initialization of the processor and memory of the system on system startup.

14. The method of claim 13, further comprising after performing the initialization, storing the SIC in a sequestered portion of the memory setup by the SIC.

15. The method of claim 14, further comprising invoking the SIC stored in the sequestered portion.

16. The method of claim 10, further comprising synthesizing a peripheral device address in a chipset and invoking the SIC via an access to the peripheral device address by the OSPM code.

17. A system comprising:

a processor including a plurality of cores and a non-volatile memory, the non-volatile memory to store semiconductor integrated code (SIC) corresponding to platform independent code of a manufacturer of the processor, the SIC including an embedded processor logic to initialize the processor and at least one communication link that couples the processor to a system memory, and an embedded memory logic to initialize the system memory, wherein the SIC is to be executed responsive to a processor reset and prior to providing control to an original equipment manufacturer (OEM) basic input/output system (BIOS), wherein the OEM is a third party to the processor manufacturer, and responsive to the processor reset, a firmware integration table (FIT) is to be accessed to determine whether a SIC entry in the FIT corresponds to a maximum revision of the SIC, an initial program loader (IPL) is to be executed, the SIC is to be executed if the IPL is executed successfully to initialize the processor, wherein a boot failure is to occur responsive to at least one of the FIT is not able to be accessed, the SIC entry does not correspond to the maximum revision, the SIC is non-authenticated, and the processor is not properly initialized;

a flash memory to store firmware of the OEM, the firmware including the OEM BIOS; and

the system memory coupled to the processor.

18. The system of claim 17, wherein the IPL is to be launched from microcode of the processor.

19. The system of claim 18, wherein the SIC is to sequester a portion of the system memory for exclusive use by the processor during system operation, wherein the sequestered portion is to be invisible to an operating system.