Hierarchical presentation techniques for a design tool
First Claim
1. A computer-readable memory or storage device storing computer-executable instructions, which when executed by a computer cause the computer to perform a method, the method comprising:
- displaying a top-level schedule for an electronic circuit design that includes one or more loops associated with the electronic circuit, the top-level schedule being divided into steps, where each step represents a clock cycle in an iteration of a loop, and wherein timing within the top-level schedule is presented relative to the top-level schedule; and
displaying a first loop schedule, nested within the top-level schedule, for a first loop of the one or more loops, wherein timing within the first loop schedule is independent of top-level clock timing and is presented relative to the first loop schedule, with the first loop schedule being divided into sub-steps, wherein each sub-step represents a clock cycle in an iteration of the first loop and the first loop schedule, including the sub-steps, is presented within a step of the top-level schedule.
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Accused Products
Abstract
A design tool hierarchically presents information about a design with nested blocks. For example, the design tool presents scheduling information for the design in a hierarchical Gantt chart. The scheduling information includes hierarchical design schedule blocks which accurately depict the timing and scheduling of the nested blocks of the design. Each of the hierarchical design schedule blocks includes control steps numbered relative to the block. The scheduling information also includes a hierarchical list of scheduled operations for the design. The hierarchical list emphasizes which operations are associated with which nested blocks. The scheduling information further includes pseudo-operation icons that are easily differentiated from real operation icons in the hierarchical Gantt chart.
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Citations
19 Claims
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1. A computer-readable memory or storage device storing computer-executable instructions, which when executed by a computer cause the computer to perform a method, the method comprising:
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displaying a top-level schedule for an electronic circuit design that includes one or more loops associated with the electronic circuit, the top-level schedule being divided into steps, where each step represents a clock cycle in an iteration of a loop, and wherein timing within the top-level schedule is presented relative to the top-level schedule; and displaying a first loop schedule, nested within the top-level schedule, for a first loop of the one or more loops, wherein timing within the first loop schedule is independent of top-level clock timing and is presented relative to the first loop schedule, with the first loop schedule being divided into sub-steps, wherein each sub-step represents a clock cycle in an iteration of the first loop and the first loop schedule, including the sub-steps, is presented within a step of the top-level schedule. - View Dependent Claims (2, 3, 4, 5)
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6. A computer-readable memory or storage device storing computer-executable instructions, which when executed by a computer cause the computer to perform a method, the method comprising:
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presenting a first level schedule for a block of a design of an electronic circuit, the block including a sub-block nested within the block of the design; and presenting second information for the sub-block of the design, wherein timing within the block is presented as independent of timing within the sub-block, and wherein the timing within the sub-block is presented as independent of the timing within the block, the timing of both the block and sub-block being associated with the timing of the electronic circuit, the timing of the sub-block being presented to show a respective scheduled position of operations of the sub-block within a range of potential locations. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A computer-readable memory or storage device storing computer-executable instructions, which when executed by a computer cause the computer to perform a method, the method comprising:
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presenting a top-level schedule that includes one or more nested loop schedules, wherein the top-level schedule is divided into control steps, wherein each control step represents a clock cycle; and presenting plural nested loop schedules for a design of an electronic circuit, each of the plural nested loop schedules under a top-level schedule including; a line of control step labels, wherein control step timing for each of the plural nested loop schedules is relative to that nested loop schedule and the control step timing for each nested loop schedule and the top-level schedule is independent of the control step timings for the other nested loop schedules and the top-level schedule, the control step timing representing one or more clock cycles in a block iteration, and one or more lines of schedule information including at least one operation icon. - View Dependent Claims (17, 18, 19)
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Specification