One-transistor pixel array with cascoded column circuit
First Claim
Patent Images
1. A device comprising:
- an array of pixels, at least some pixels in the array of pixels comprising;
a chemically-sensitive field-effect transistor including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer; and
a cascode transistor including a source terminal, a drain terminal and a gate terminal, wherein the source terminal of the cascode transistor is directly connected to the drain terminal of the chemically-sensitive field-effect transistor; and
a plurality of column lines and a plurality of row lines coupled to pixels in the array of pixels, wherein each column line in the plurality of column lines is directly connected to drain terminals of cascode transistors of a corresponding first plurality of pixels in the array, and wherein each row line in the plurality of row lines is directly connected to the source terminals of chemically-sensitive field-effect transistors of a corresponding second plurality of pixels in the array.
1 Assignment
0 Petitions
Accused Products
Abstract
To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.
325 Citations
18 Claims
-
1. A device comprising:
-
an array of pixels, at least some pixels in the array of pixels comprising; a chemically-sensitive field-effect transistor including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer; and a cascode transistor including a source terminal, a drain terminal and a gate terminal, wherein the source terminal of the cascode transistor is directly connected to the drain terminal of the chemically-sensitive field-effect transistor; and a plurality of column lines and a plurality of row lines coupled to pixels in the array of pixels, wherein each column line in the plurality of column lines is directly connected to drain terminals of cascode transistors of a corresponding first plurality of pixels in the array, and wherein each row line in the plurality of row lines is directly connected to the source terminals of chemically-sensitive field-effect transistors of a corresponding second plurality of pixels in the array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A device comprising:
-
an array of chemically-sensitive field-effect transistors, at least some chemically-sensitive field-effect transistors in the array of chemically-sensitive field-effect transistors including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer; a plurality of column lines and a plurality of row lines coupled to chemically-sensitive field-effect transistors in the array of chemically-sensitive field-effect transistors, wherein each column line in the plurality of column lines is directly connected to drain terminals of a corresponding plurality of chemically-sensitive field-effect transistors in the array, and each row line in the plurality of row lines is directly connected to source terminals of a corresponding second plurality of chemically-sensitive field-effect transistors in the array; and respective cascode transistors coupled to corresponding column lines in the plurality of column lines, wherein a given cascode transistor includes a source terminal, a drain terminal and a gate terminal, and the source terminal of the given cascode transistor is coupled to the corresponding column line. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
-
Specification