Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices

• US 8,524,592 B1
• Filed: 08/13/2012
• Issued: 09/03/2013
• Est. Priority Date: 08/13/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), International Business Machines Corporation
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Cheng, Kangguo, Khakifirooz, Ali, Cai, Xiuyu Jr.
• Primary Examiner(s): Le, Thao
• Assistant Examiner(s): IDA, GEOFFREY H
• Application Number:
  US13/584,055
• Time in Patent Office: 386 Days
• Field of Search: 438/595, 257/387
• US Class Current: 438/595
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Claims

1. A method, comprising:

forming a sacrificial gate structure above a semiconducting substrate, said sacrificial gate structure comprising at least a sacrificial gate electrode that has a plurality of sidewalls;

forming at least one sacrificial sidewall spacer adjacent said sacrificial gate electrode;

performing at least one etching process to remove at least a portion of said sacrificial sidewall spacer and thereby expose at least a portion of said sidewalls of said sacrificial gate electrode;

after performing said etching process, forming a liner layer on said exposed sidewalls of said sacrificial gate electrode;

forming at least one layer of sacrificial gap fill material above said liner layer;

performing at least one process operation to expose an upper surface of said sacrificial gate electrode;

after exposing said upper surface of said sacrificial gate electrode, removing at least said sacrificial gate electrode to thereby define a gate cavity that is laterally defined by said liner layer;

forming a replacement gate structure in said gate cavity;

after forming said replacement gate structure, removing said at least one layer of sacrificial gap fill material; and

forming a low-k sidewall spacer adjacent said liner layer.

2. The method of claim 1, wherein said low-k sidewall spacer is comprised of a material having a k value less than 7.

3. The method of claim 1, wherein said liner layer is comprised of silicon nitride or silicon oxynitride.

4. The method of claim 3, wherein said at least one layer of sacrificial gap fill material is comprised of a single layer of silicon dioxide.

5. The method of claim 3, wherein said at least one layer of sacrificial gap fill material is comprised of a first layer of amorphous silicon positioned above said substrate and a second layer of silicon dioxide positioned above said first layer of amorphous silicon.

6. The method of claim 1, wherein said sacrificial gate structure is comprised of a silicon dioxide gate insulation layer and a polysilicon gate electrode positioned above said gate insulation layer.

7. The method of claim 1, wherein said replacement gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

8. The method of claim 1, wherein said step of removing at least said sacrificial gate electrode comprises performing at least one etching process to remove at least said sacrificial gate electrode.

9. The method of claim 1, wherein said step of performing said at least one process operation to expose an upper surface of said sacrificial gate electrode comprises performing at least one chemical mechanical polishing process to expose said upper surface of said sacrificial gate electrode.

10. The method of claim 1, wherein said step of forming said low-k spacer adjacent said liner layer comprises depositing a layer of low-k insulating material above and on said liner layer and performing an anisotropic etching process on said layer of low-k insulating material.

11. A method, comprising:

forming a sacrificial gate structure above a semiconducting substrate, said sacrificial gate structure comprising at least a sacrificial gate electrode that has a plurality of sidewalls;

forming at least one sacrificial sidewall spacer on said sacrificial gate electrode;

performing at least one etching process to remove at least a portion of said sacrificial sidewall spacer and thereby expose a portion of said sidewalls of said sacrificial gate electrode;

after performing said etching process, forming a liner layer comprised of silicon nitride or silicon oxynitride on said exposed sidewalls of said sacrificial gate electrode;

forming at least one layer of sacrificial gap fill material above said liner layer;

performing at least one process operation to expose an upper surface of said sacrificial gate electrode;

after exposing said upper surface of said sacrificial gate electrode, removing at least said sacrificial gate electrode to thereby define a gate cavity that is laterally defined by said liner layer;

forming a replacement gate structure in said gate cavity;

after forming said replacement gate structure, removing said at least one layer of sacrificial gap fill material; and

forming a low-k sidewall spacer on said liner layer, wherein said low-k sidewall spacer is comprised of a material having a dielectric constant less than 7.

12. The method of claim 11, wherein said at least one layer of sacrificial gap fill material is comprised of a single layer of silicon dioxide.

13. The method of claim 11, wherein said at least one layer of sacrificial gap fill material is comprised of a first layer of amorphous silicon positioned above said substrate and a second layer of silicon dioxide positioned above said first layer of amorphous silicon.

14. The method of claim 11, wherein said sacrificial gate structure is comprised of a silicon dioxide gate insulation layer and a polysilicon gate electrode positioned above said gate insulation layer.

15. The method of claim 11, wherein said replacement gate structure comprises a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal.

16. The method of claim 11, wherein said step of removing at least said sacrificial gate electrode comprises performing at least one etching process to remove at least said sacrificial gate electrode.

17. The method of claim 11, wherein said step of performing said at least one process operation to expose an upper surface of said sacrificial gate electrode comprises performing at least one chemical mechanical polishing process to expose said upper surface of said sacrificial gate electrode.

18. The method of claim 11, wherein said step of forming said low-k spacer on said liner layer comprises depositing a layer of low-k insulating material above and on said liner layer and performing an anisotropic etching process on said layer of low-k insulating material.