Integrated circuit (IC) test probe

• US 8,525,168 B2
• Filed: 07/11/2011
• Issued: 09/03/2013
• Est. Priority Date: 07/11/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dang, Bing, Knickerbocker, John U., Liu, Yang
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/179,868
• Publication Number:
  US 20130015440A1
• Time in Patent Office: 785 Days
• Field of Search: 438/694, 438/719, 438734-736, 438/689, 438/696, 438/52, 257/734, 257/48, 257/E23.01
• US Class Current: 257/48
• CPC Class Codes: G01R 1/06761 related to layers
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 μm). The probe tips may be stiffened with SiO₂ (and optionally silicon) extending along the sidewalls. A redistribution layer connects individual test probe tips externally. The probe tips may be capped with a hardening cap that also caps stiffening SiO₂ and silicon along the tip sidewall.

Claims

1. A method of forming test probes, said method comprising:

forming a plurality of vias through a semiconductor layer, said plurality of vias defining plurality of probes, a semiconductor core remaining in the center of each of said probe, the plurality of probes being a test head;

etching said semiconductor layer, said plurality of probes extending above the surface of said etched semiconductor layer, portions of probes above said surface being probe tips; and

mounting said test head in a test fixture.

2. A method of forming test probes as in claim 1, wherein forming said plurality of vias forms annular vias, each annular via being a probe, and etching said semiconductor layer comprises etching notches in the end of said annular probes, etched said probes having notched tips.

3. A method of forming test probes as in claim 1, wherein etching said semiconductor layer comprises:

masking said surface, said surface remaining exposed at the test head such that the upper end of each via remains exposed; and

etching exposed areas, said semiconductor layer being sub-etched in said test head, sub-etching said semiconductor layer defining said probe tips.

4. A method of forming test probes as in claim 1, wherein said semiconductor layer is a silicon wafer and forming said plurality of probes through said semiconductor layer, comprises:

etching a plurality of vias to a selected depth in a surface of said silicon wafer, each of said plurality of vias terminating above the lower surface of said wafer;

oxidizing the sidewalls of said plurality of vias; and

filling said plurality of vias with conductive material.

5. A method of forming test probes as in claim 3, wherein etching exposed areas further comprising stiffening said probe tips.

6. A method of forming test probes as in claim 3, wherein before etching said semiconductor layer, stiffening said probe tips comprises:

forming a metal layer on said surface; and

patterning said metal layer to said plurality of probes such that a metal cap overlaps all sides of each via extending above said surface.

7. A method of forming test probes as in claim 5, wherein after etching exposed areas stiffening said probe tips comprises building up semiconductor along said probe tips.

8. A method of forming test probes as in claim 6, wherein forming said plurality of probes forms annular probes;

patterning said metal forms an annular cap at each annular probe tip, each annular cap having a smaller inside diameter than the diameter of the semiconductor core and a larger outside diameter than said each annular via; and

etching said semiconductor layer leaves semiconductor material along sidewalls of said probe tip capped by a respective annular cap.

9. A method of forming test probe heads for probing integrated circuit (IC) chips, said method comprising:

etching an array of vias to a selected depth in a surface of a semiconductor wafer, each of said vias in said array terminating above the opposite surface of said wafer;

insulating the sidewalls of said vias;

filling said vias with conductive material;

etching said semiconductor wafer at said array, said semiconductor wafer being sub-etched such that said array vias extend from said sub-etched surface, sub-etched via portions being individual test probe tips;

separating said array from said wafer, said separated array being a test head; and

mounting said test head in a test fixture.

10. A method of forming test probe heads as in claim 9, wherein said wafer is a silicon wafer, said surface being oxidized with said sidewalls, and filling said vias comprises forming a metal layer on said oxidized surface, said metal layer being said conductive material filling said vias.

11. A method of forming test probe heads as in claim 10, wherein etching said wafer comprises:

removing horizontal portions of said metal layer from said wafer;

removing oxide from said surface;

masking said surface, said surface remaining exposed at the test head such that the upper end of each via remains exposed; and

etching said surface in exposed areas, said wafer being sub-etched in said array of vias.

12. A method of forming test probe heads as in claim 10, wherein etching said surface comprises:

masking said metal layer, said metal layer remaining exposed at the test head;

removing unmasked portions of said metal layer from said oxidized surface;

removing exposed oxide from said surface; and

etching exposed areas of said wafer, said individual test probe tips being nail headed and said wafer being sub-etched in said array of nail headed test probe tips.

13. A method of forming test probe heads as in claim 10, wherein etching said surface comprises:

removing horizontal portions of said metal layer from said wafer;

attaching a handle layer to oxide on said surface;

removing the portion of said wafer between the bottom of said vias and said other surface, the other end of each via being exposed; and

etching said wafer at exposed vias, said wafer being sub-etched at the bottom of said array of vias, the bottom end of said array of vias being probe tips for a probe head.

14. A method of forming test probe heads as in claim 10, wherein forming said plurality of vias forms annular probes and etching said wafer further comprises etching notches in sub-etched said annular test probe tips.

15. A method of forming test probe heads as in claim 11, wherein subsequent to sub-etching said surface, said method further comprises stiffening said individual test probe tips with silicon.

16. A test probe head comprising:

a semiconductor layer;

an array of vias extending though said semiconductor layer, exiting one surface of said semiconductor layer, and defining a plurality of probes, each probe including a semiconductor core, individual via portions above said surface being individual test probe tips; and

a redistribution layer connecting individual test probes externally.

17. A test probe head as in claim 16, wherein the semiconductor layer is a silicon layer, each said semiconductor core is a silicon core, and said test probe tips are on a pitch at or less than fifty microns (50 μ

m).

18. A test probe head as in claim 17, wherein one or more of said plurality of probes is an annular via and the test probe tip of at least one annular test probe is notched.

19. A test probe head as in claim 17, wherein one or more of said vias is a group of vias having a rectangular cross section.

20. A test probe head as in claim 17, wherein silicon sidewalls extends along the dielectric sidewalls of said test probe tips.

21. A test probe head as in claim 20, further comprising a metal cap on each test probe tip, wherein said silicon along the dielectric sidewall of said each test probe tip is capped by said metal cap.

22. A test probe head for probing integrated circuit (IC) chips, said test head comprising:

a silicon layer;

an array of metal vias defining a plurality of individual test probes, on a pitch at or less than fifty microns (50 μ

m) extending through and exiting one surface of said silicon layer, via portions exiting said one surface being individual test probe tips;

a silicon core in each test probe;

silicon sidewalls extending from one said silicon core along the sidewalls of said test probe tips; and

a redistribution layer connecting individual test probes externally.

23. A test probe head as in claim 22, wherein one or more of said individual test probes is an annular via and the test probe tip of at least one annular test probe is notched.

24. A test probe head as in claim 22, wherein one or more of said individual test probes is a group of vias separated by said silicon core and each having a rectangular cross section.

25. A test probe head as in claim 24, further comprising a tungsten cap on each test probe tip, said tungsten cap capping said silicon sidewalls along the sidewall of said each test probe tip.