Semiconductor structure having a wetting layer

• US 8,525,232 B2
• Filed: 08/10/2011
• Issued: 09/03/2013
• Est. Priority Date: 08/10/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nogami, Takeshi, Wong, Keith K. H., Yang, Chih-Chao
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US13/206,586
• Publication Number:
  US 20130037865A1
• Time in Patent Office: 755 Days
• Field of Search: 257/197, 257/E21.171, 438/259, 438/596
• US Class Current: 257/197
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/32056 Deposition of conductive or semi-conductive organic layers H01L21/32058 takes precedence
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process.

Claims

1. A semiconductor structure comprising:

a semiconductor substrate; and

a metal gate structure formed in a trench or via on the semiconductor substrate, the metal gate structure comprising;

a gate dielectric;

a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and

an aluminum layer to fill the remainder of the trench or via.

2. The semiconductor structure of claim 1 wherein the wetting layer is oxygen free.

3. The semiconductor structure of claim 1 wherein the wetting layer has a thickness of 5 to 20 angstroms.

4. The semiconductor structure of claim 1 further comprising a metallic layer between the gate dielectric and the wetting layer.

5. The semiconductor structure of claim 4 wherein the metallic layer is a workfunction metal and the semiconductor structure is a PFET, the workfunction metal including a dual layer comprising a first layer selected from the group consisting of titanium nitride, ruthenium and tantalum nitride and a second layer selected from the group consisting of tantalum carbide and titanium aluminum.

6. The semiconductor structure of claim 5 wherein the wetting layer is directly on the second layer of the workfunction metal.

7. The semiconductor structure of claim 4 wherein the metallic layer is a workfunction metal and the semiconductor structure is an NFET, the workfunction metal selected from the group consisting of tantalum carbide and titanium aluminum.

8. The semiconductor structure of claim 7 wherein the wetting layer is directly on the workfunction metal.

9. A method of forming a semiconductor structure comprising:

forming a dummy gate on a semiconductor substrate;

forming a spacer on the dummy gate structure;

removing the dummy gate to form a trench or via;

depositing a gate dielectric in the trench or via;

depositing a wetting layer selected from the group consisting of cobalt and nickel to line the trench or via, the wetting layer formed by cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process; and

depositing aluminum to fill the remainder of the trench or via.

10. The method of claim 9 wherein the cobalt amidinate or nickel amidinate has the formula [M(AMD)2], and the structure

11. The method of claim 9 wherein the wetting layer has an oxygen content of no more than about 200 ppm (parts per million) oxygen.

12. The method of claim 9 wherein the wetting layer is oxygen free.

13. The method of claim 9 wherein depositing aluminum comprises depositing aluminum by a physical vapor deposition process.

14. The method of claim 13 wherein the aluminum is deposited directly on the wetting layer.

15. The method of claim 9 wherein depositing aluminum comprises depositing aluminum by a chemical vapor deposition process followed by depositing aluminum by a physical vapor deposition process.

16. The method of claim 9 wherein between depositing a gate dielectric and depositing a cobalt layer, further comprising depositing a metallic layer wherein the metallic layer is a workfunction metal and the semiconductor structure is a PFET, the workfunction metal including a dual layer comprising a first layer selected from the group consisting of titanium nitride, ruthenium and tantalum nitride and a second layer selected from the group consisting of tantalum carbide and titanium aluminum.

17. The method of claim 16 wherein depositing a wetting layer includes depositing a wetting layer directly on the second layer.

18. The method of claim 9 wherein between depositing a gate dielectric and depositing a wetting layer, further comprising depositing a metallic layer wherein the metallic layer is a workfunction metal and the semiconductor structure is an NFET, the workfunction metal selected from the group consisting of tantalum carbide and titanium aluminum.

19. The method of claim 18 wherein depositing a wetting layer includes depositing a wetting layer directly on the workfunction metal.

20. A method of forming a semiconductor structure comprising:

forming a dummy gate on a semiconductor substrate;

forming a spacer on the dummy gate structure;

removing the dummy gate to form a trench or via;

depositing a gate dielectric in the trench or via;

depositing a wetting layer selected from the group consisting of cobalt and nickel to line the trench or via, the wetting layer having an oxygen content of no more than about 200 ppm (parts per million) oxygen and formed by depositing cobalt amidinate or nickel amidinate by a chemical vapor deposition process wherein the cobalt amidinate or nickel amidinate has the formula M(AMD)2], and the structure