Super junction device with deep trench and implant

• US 8,525,260 B2
• Filed: 03/19/2010
• Issued: 09/03/2013
• Est. Priority Date: 03/19/2010
• Status: Active Grant

• Current Assignee: Monolithic Power Systems Incorporated
• Original Assignee: Monolithic Power Systems Incorporated
• Inventors: Li, Tiesheng, Hsing, Michael R., Xiao, Deming
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US12/728,044
• Publication Number:
  US 20110227147A1
• Time in Patent Office: 1,264 Days
• Field of Search: 257/341, 257/328, 257/329
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

RESURF effect devices with both relatively deep trenches and relatively deep implants are described herein. Also, methods of fabricating such devices are described herein. A RESURF effect device may include alternating regions of first and second conductivity types where each of the second regions includes an implant region formed into a trench region of the second region.

Claims

1. A device, comprising:

a substrate;

a plurality of first regions of a first conductivity type formed on the substrate; and

a plurality of second regions of a second conductivity type formed on the substrate and interleaved with the plurality of first regions, wherein each of the second regions includes;

an implant region implanted between the substrate and a trenched region;

a conductive column of the second conductivity type formed into the trenched region; and

an insulative barrier configured to insulate the conductive column from the implant region and from the first regions adjacent to the second region.

2. The device of claim 1, wherein the substrate is an N+ substrate, the first regions are N regions, and the second regions are P regions.

3. The device of claim 1, wherein first conductivity type is N-type and the second conductivity type is P-type.

4. The device of claim 1, wherein the conductive column includes doped polysilicon.

5. The device of claim 1, wherein each of the first regions is formed as a column and is vertically disposed between the substrate and a third region of the second conductivity type.

6. The device of claim 5, wherein each of the first regions are electrically shorted to respective third regions.

7. The device of claim 1, wherein the substrate includes at least two layers, and wherein dopant concentrations of each of the two layers are different.

8. The device of claim 1, wherein the insulation barriers include silicon dioxide.

9. The device of claim 1, wherein the insulation barriers include spin-on glass, a flowable oxide, or an organic material.

10. The device of claim 1, wherein the trench regions extends into an active layer of the device.

11. The device of claim 1, wherein the device is a metal-oxide-semiconductor field-effect transistor.

12. The device of claim 1, wherein the plurality of first regions and the plurality of second regions form a drift region of a semiconductor device.

13. The device of claim 1, wherein the device is a metal-oxide-semiconductor field-effect transistor, and wherein the device further comprises:

drain regions of the first conductivity type;

source regions; and

gate regions.