Semiconductor structure with improved channel stack and method for fabrication thereof
First Claim
1. A method for fabricating a transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising:
- in a first region having a first doped well providing a foundation for a PMOS transistor element;
ion implanting in the semiconductor substrate a first doped screening layer in contact with the first doped well, the first doped screening layer including antimony;
ion implanting in the semiconductor substrate a first doped threshold voltage control layer in contact with the first doped screening layer;
in a second region having a second doped well providing a foundation for an NMOS transistor element;
ion implanting in the semiconductor substrate a second doped screening layer in contact with the second well;
ion implanting in the semiconductor substrate a second doped threshold voltage control layer in contact with the second doped screening layer;
forming a third layer on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, by way of multiple blanket undoped epitaxial growth to establish an intrinsic channel for each of the PMOS and NMOS transistor elements;
wherein the third layer of the PMOS transistor element is formed with a different channel thickness than the third layer of the NMOS transistor element.
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Abstract
A method for fabricating a semiconductor structure with a channel stack includes forming a screening layer under a gate of a PMOS transistor element and a NMOS transistor element, forming a threshold voltage control layer on the screening layer, and forming an epitaxial channel layer on the threshold control layer. At least a portion of the epitaxial channel layers for the PMOS transistor element and the NMOS transistor element are formed as a common blanket layer. The screening layer for the PMOS transistor element may include antimony as a dopant material that may be inserted into the structure prior to or after formation of the epitaxial channel layer.
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Citations
8 Claims
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1. A method for fabricating a transistor structure with a channel stack, the transistor structure having a semiconductor substrate with a plurality of pre-formed doped wells formed therein, comprising:
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in a first region having a first doped well providing a foundation for a PMOS transistor element; ion implanting in the semiconductor substrate a first doped screening layer in contact with the first doped well, the first doped screening layer including antimony; ion implanting in the semiconductor substrate a first doped threshold voltage control layer in contact with the first doped screening layer; in a second region having a second doped well providing a foundation for an NMOS transistor element; ion implanting in the semiconductor substrate a second doped screening layer in contact with the second well; ion implanting in the semiconductor substrate a second doped threshold voltage control layer in contact with the second doped screening layer; forming a third layer on the semiconductor substrate, separate from and on top of the first and second doped threshold voltage control layers, by way of multiple blanket undoped epitaxial growth to establish an intrinsic channel for each of the PMOS and NMOS transistor elements; wherein the third layer of the PMOS transistor element is formed with a different channel thickness than the third layer of the NMOS transistor element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification