Chip assembly with frequency extending device

• US 8,525,313 B2
• Filed: 03/12/2012
• Issued: 09/03/2013
• Est. Priority Date: 04/10/2008
• Status: Expired due to Fees

• Current Assignee: Semtech Corporation
• Original Assignee: Semtech Corporation
• Inventors: Lao, Binneg Y., Chen, William W.
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US13/418,201
• Publication Number:
  US 20120168928A1
• Time in Patent Office: 540 Days
• Field of Search: 257/666, 257/676, 257/734, 257/E23.031, 257/E23.032, 257/E23.033, 257/E23.034, 257/E23.035
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48011 Length
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49524 the additional leads being a tape carrier or flat leads
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A chip assembly includes a chip, a paddle, an interface layer, a frequency extending device, and lands. The chip has contacts. The interface layer is disposed between the chip and the paddle. The frequency extending device has at least a conductive layer and a dielectric layer. The conductive layer has conductive traces. The frequency extending device is disposed adjacent to the side of the chip and overlying the paddle. The lands are disposed adjacent to the side of the paddle. The contacts are connected to the conductive traces. The conductive traces are connected to the lands. The frequency extending device is configured to reduce impedance discontinuity such that the impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by bond wires each having a length greater than or substantially equal to the distance between the contacts and the lands.

Claims

1. A chip assembly, comprising:

a chip having a front surface, a rear surface and a side, the chip having conductive contacts on the front surface;

a conductive paddle coupled to the chip, the conductive paddle having a front surface, a rear surface and a side;

a conductive interface layer disposed between the rear surface of the chip and the front surface of the conductive paddle, the conductive interface layer coupled to the rear surface of the chip and coupled to the front surface of the conductive paddle;

a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the conductive paddle, an interface layer disposed between the frequency extending device and the conductive paddle; and

a plurality of conductive lands disposed at least partially adjacent to the side of the conductive paddle, at least one of the conductive contacts connected to at least one of the one or more conductive traces, the at least one of the one or more conductive traces connected to at least one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that an impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires each having a length substantially equal to a distance between one of the conductive contacts of the chip and a corresponding one of the plurality of conductive lands,

wherein the frequency extending device completely surrounds the side and the front surface of the chip.

2. The chip assembly according to claim 1, wherein the frequency extending device has a front surface, a rear surface and a side, the frequency extending device further has a second conductive layer and one or more vias,

wherein the first conductive layer is disposed on the front surface of the frequency extending device, the second conductive layer is disposed on the rear surface of the frequency extending device, and the one or more vias extend along the side of the frequency extending device.

3. The chip assembly according to claim 2, wherein at least a first one of the one or more conductive traces of the first conductive layer is a high frequency signal line,

wherein at least a second one of the one or more conductive traces of the first conductive layer is a ground trace, the second conductive layer has a block of a ground trace, and the one or more vias are connected to the at least second one of the one or more conductive traces of the first conductive layer and to the block of a ground trace.

4. The chip assembly according to claim 3, wherein at least a third one of the one or more conductive traces of the first conductive layer is a ground trace, and the first one of the one or more conductive traces is disposed laterally between the second one and the third one of the one or more conductive traces.

5. The chip assembly according to claim 1, wherein the frequency extending device surrounds sides of the chip, and the plurality of conductive lands surround sides of the frequency extending device.

6. The chip assembly according to claim 1, wherein at least one of the one or more conductive traces has one or more matching elements extending from one or more sides of the at least one of the one or more conductive traces, the one or more matching elements configured to reduce the impedance discontinuity further.

7. The chip assembly according to claim 1, wherein a pitch between the conductive contacts is smaller than a pitch between the plurality of conductive lands.

8. The chip assembly according to claim 1, wherein the frequency extending device is configured to carry one or more high frequency signals and ground.

9. The chip assembly according to claim 1, further comprising a plurality of solder balls,

wherein the plurality of solder balls connect the conductive contacts of the chip to conductive traces of the frequency extending device.

10. The chip assembly according to claim 1, further comprising a plurality of solder balls,

wherein the frequency extending device further has a second conductive layer and one or more vias,

wherein the second conductive layer has one or more conductive traces,

wherein at least a first one of the plurality of solder balls is connected to at least a first one of the conductive contacts of the chip and to at least a first one of the one or more conductive traces of the first conductive layer of the frequency extending device,

wherein at least a first one of the one or more vias is connected to the first one of the one or more conductive traces of the first conductive layer and to at least a first one of the one or more conductive traces of the second conductive layer of the frequency extending device.

11. The chip assembly according to claim 10, wherein the first one of the one or more conductive traces of the second conductive layer of the frequency extending device is connected to the conductive paddle and to at least a first one of the plurality of conductive lands.

12. The chip assembly according to claim 10, wherein the first one of the one or more conductive traces of the second conductive layer of the frequency extending device is connected to at least a first one of the plurality of conductive lands.

13. The chip assembly according to claim 10, wherein the frequency extending device further has a third conductive layer having one or more conductive traces,

wherein the first one of the one or more conductive traces of the first conductive layer is connected to the first one of the one or more vias,

wherein the first one of the one or more vias is connected to at least a first one of the one or more conductive traces of the third conductive layer,

wherein the first one of the one or more conductive traces of the third conductive layer is connected to at least a second one of the one or more vias, and

wherein the second one of the one or more vias is connected to at least the first one of the one or more conductive traces of the second conductive layer of the frequency extending device.

14. The chip assembly according to claim 1, wherein the frequency extending device has a first overhang portion, a base portion, and a second overhang portion,

wherein the first overhang portion is disposed at least partially overlying the chip,

wherein the base portion is disposed at least partially overlying the conductive paddle, and

wherein the second overhang portion is disposed at least partially overlying the plurality of conductive lands.

15. The chip assembly according to claim 1, wherein the chip is completely encapsulated by the frequency extending device and the conductive paddle.

16. A chip assembly, comprising:

a chip having a front surface, a rear surface and a side, the chip having conductive contacts on the front surface;

a conductive paddle coupled to the chip, the conductive paddle having a front surface, a rear surface and a side;

a conductive interface layer disposed between the rear surface of the chip and the front surface of the conductive paddle, the conductive interface layer coupled to the rear surface of the chip and coupled to the front surface of the conductive paddle;

a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the conductive paddle, an interface layer disposed between the frequency extending device and the conductive paddle;

a plurality of conductive lands disposed at least partially adjacent to the side of the conductive paddle, at least one of the conductive contacts connected to at least one of the one or more conductive traces, the at least one of the one or more conductive traces connected to at least one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that an impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires each having a length substantially equal to a distance between one of the conductive contacts of the chip and a corresponding one of the plurality of conductive lands; and

a plurality of solder balls,

wherein the frequency extending device further has a second conductive layer and one or more vias,

wherein the second conductive layer has one or more conductive traces,

wherein at least a first one of the plurality of solder balls is connected to at least a first one of the conductive contacts of the chip and to at least a first one of the one or more conductive traces of the first conductive layer of the frequency extending device,

wherein at least a first one of the one or more vias is connected to the first one of the one or more conductive traces of the first conductive layer and to at least a first one of the one or more conductive traces of the second conductive layer of the frequency extending device,

wherein the first one of the one or more conductive traces of the second conductive layer of the frequency extending device is connected to at least a first one of the plurality of conductive lands,

wherein the frequency extending device further has a third conductive layer,

wherein the third conductive layer has one or more conductive traces, the first one of the one or more conductive traces of the first conductive layer of the frequency extending device is disposed between at least a first one of the one or more conductive traces of the third conductive layer and at least a second one of the one or more conductive traces of the second conductive layer of the frequency extending device,

wherein the second one of the one or more conductive traces of the second conductive layer is connected to the conductive paddle, and

wherein the first one of the one or more conductive traces of the third conductive layer is a ground trace.

17. The chip assembly according to claim 16, wherein the frequency extending device completely surrounds the side and the front surface of the chip.

18. A chip assembly, comprising:

a chip having a front surface, a rear surface and a side, the chip having conductive contacts on the front surface;

a conductive paddle coupled to the chip, the conductive paddle having a front surface, a rear surface and a side;

a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the conductive paddle, an interface layer disposed between the frequency extending device and the conductive paddle;

a plurality of conductive lands disposed at least partially adjacent to the side of the conductive paddle, at least one of the conductive contacts connected to at least one of the one or more conductive traces, the at least one of the one or more conductive traces connected to at least one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that an impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires each having a length substantially equal to a distance between one of the conductive contacts of the chip and a corresponding one of the plurality of conductive lands; and

wherein the frequency extending device further has a second conductive layer,

wherein the second conductive layer has one or more conductive traces,

wherein the frequency extending device has a first front surface, a second front surface, a side, and a rear surface,

wherein the first front surface of the frequency extending device faces away from the front surface of the chip, the second front surface of the frequency extending device faces toward the front surface of the chip, the side of the frequency extending device faces toward the side of the chip, and the rear surface of the frequency extending device faces toward the conductive paddle,

wherein at least a portion of a first one of the one or more conductive traces of the first conductive layer is disposed on the second front surface of the frequency extending device, and

wherein at least a portion of a first one of the one or more conductive traces of the second conductive layer of the frequency extending device is disposed on the rear surface of the frequency extending device.

19. The chip assembly according to claim 18, wherein at least a portion of the first one of the one or more conductive traces of the first conductive layer is disposed on an inner surface of the frequency extending device.

20. A chip assembly, comprising:

a chip having a front surface, a rear surface and a side, the chip having conductive contacts;

a substrate coupled to the chip, the substrate having a front surface, a rear surface and a side;

an interface layer disposed between the rear surface of the chip and the front surface of the substrate;

a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the substrate; and

a plurality of conductive lands, at least one of the conductive contacts of the chip connected to one of the one or more conductive traces of the frequency extending device, the at least one of the one or more conductive traces of the frequency extending device connected to one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that an impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires if such one or more bond wires were to be used in place of the frequency extending device,

wherein the frequency extending device completely surrounds the side and the front surface of the chip.

21. A chip assembly, comprising:

a chip having a front surface, a rear surface and a side, the chip having conductive contacts on the front surface;

a conductive paddle coupled to the chip, the conductive paddle having a front surface, a rear surface and a side;

a conductive interface layer disposed between the rear surface of the chip and the front surface of the conductive paddle, the conductive interface layer coupled to the rear surface of the chip and coupled to the front surface of the conductive paddle;

a frequency extending device having at least a first conductive layer and a first dielectric layer, the first conductive layer having one or more conductive traces, the frequency extending device disposed at least partially adjacent to the side of the chip and disposed at least partially overlying the conductive paddle, an interface layer disposed between the frequency extending device and the conductive paddle;

a plurality of solder balls that connect the conductive contacts of the chip to conductive traces of the frequency extending device; and

a plurality of conductive lands disposed at least partially adjacent to the side of the conductive paddle, at least one of the conductive contacts connected to at least one of the one or more conductive traces, the at least one of the one or more conductive traces connected to at least one of the plurality of conductive lands, the frequency extending device configured to reduce impedance discontinuity such that an impedance discontinuity produced by the frequency extending device is less than an impedance discontinuity that would be produced by one or more bond wires each having a length substantially equal to a distance between one of the conductive contacts of the chip and a corresponding one of the plurality of conductive lands,

wherein the chip is completely encapsulated by the frequency extending device and the conductive paddle.

22. The chip assembly according to claim 21, wherein the front surface of the chip faces away from the conductive paddle.