Chip with sintered connections to package

• US 8,525,338 B2
• Filed: 06/07/2011
• Issued: 09/03/2013
• Est. Priority Date: 06/07/2011
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Sato, Hiroaki, Hashimoto, Kiyoaki, Nakadaira, Yoshikuni, Masuda, Norihito, Haba, Belgacem, Mohammed, Ilyas, Damberg, Philip
• Primary Examiner(s): Luke, Daniel
• Assistant Examiner(s): Ahmad, Khaja
• Application Number:
  US13/154,778
• Publication Number:
  US 20120313264A1
• Time in Patent Office: 819 Days
• Field of Search: 257/786, 257/E21.504, 257/E23.039, 257/E23.055, 257/784, 257/520, 257/698, 257/746, 257/773, 257/E23.018, 257/E23.166, 257/E23.025, 257/E23.04, 257/E23.133, 257/E23.109, 438/123
• US Class Current: 257/746
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/49517 Additional leads
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A microelectronic package and method of making same are provided. The package includes a substrate having first and second opposed surfaces, an edge surface extending therebetween, a plurality of terminals, and a plurality of conductive elements electrically connected with the terminals. The edge surface can be disposed at a periphery of the substrate or can be the edge surface of an aperture within the substrate. A microelectronic element has a front face and contacts thereon, with at least some of the contacts being adjacent to the edge surface of the substrate. A dielectric material overlies the edge surface of the substrate and defines a sloping surface between the front face of the microelectronic element and the substrate. A conductive matrix material defines a plurality of conductive interconnects extending along the sloping surface. The conductive interconnects electrically interconnect respective ones of the contacts with the conductive elements.

Claims

1. A microelectronic package comprising:

a substrate having first and second opposed surfaces and an edge surface extending therebetween, the substrate having a plurality of terminals and a plurality of conductive elements electrically connected with the terminals;

a microelectronic element having a front face and contacts thereon, at least some of the contacts adjacent to the edge surface of the substrate;

a dielectric material overlying the edge surface of the substrate and defining a sloping surface between the front face of the microelectronic element and the substrate, the dielectric material being other than an adhesive layer between the microelectronic element and the substrate; and

a conductive matrix material defining a plurality of conductive interconnects extending along the sloping surface, the conductive interconnects electrically interconnecting respective ones of the contacts with the conductive elements.

2. The microelectronic package of claim 1, further comprising an adhesive layer bonding the first surface of the substrate with the front face of the microelectronic element.

3. The microelectronic package of claim 1, wherein the edge surface is disposed at a periphery of the substrate.

4. The microelectronic package of claim 1, wherein the substrate includes an aperture extending between the first and second opposed surfaces, and wherein the edge surface is an edge surface of the aperture.

5. The microelectronic package of claim 1, wherein the substrate includes a dielectric element, and the conductive elements extend along a surface thereof.

6. The microelectronic package of claim 5, wherein the conductive elements extend along a surface of the dielectric element facing away from the microelectronic element.

7. The microelectronic package of claim 1, wherein the substrate is a lead frame, and wherein the conductive elements are fingers of the lead frame.

8. The microelectronic package of claim 1, wherein the substrate includes an element having a coefficient of thermal expansion of less than 8 parts per million per degree Celsius.

9. The microelectronic package of claim 8, wherein the conductive elements extend along a surface of the substrate facing away from the microelectronic element.

10. The microelectronic package of claim 1, wherein the sloping surface extends between the front face of the microelectronic element and the edge surface of the substrate.

11. The microelectronic package of claim 1, wherein at least a portion of the edge surface is not covered by the dielectric material.

12. The microelectronic package of claim 1, wherein the dielectric material covers the entire edge surface of the substrate.

13. The microelectronic package of claim 12, wherein the dielectric material covers at least a portion of the second surface of the substrate.

14. A system comprising a structure according to claim 1 and one or more other electronic components electrically connected to the structure.

15. A system as claimed in claim 14 further comprising a housing, said structure and said other electronic components being mounted to said housing.

16. A method of making a microelectronic package comprising:

providing a substrate having first and second opposed surfaces and an edge surface extending therebetween, the substrate having a plurality of terminals and a plurality of conductive elements electrically connected with the terminals;

mounting a microelectronic element to the substrate, the microelectronic element having a front face and contacts thereon, such that at least some of the contacts of the microelectronic element are adjacent to the edge surface of the substrate;

depositing a dielectric material overlying the edge surface of the substrate and defining a sloping surface between the front face of the microelectronic element and the substrate, the dielectric material being other than an adhesive layer between the microelectronic element and the substrate; and

depositing a conductive matrix material defining respective conductive interconnects extending along the sloping surface, the conductive interconnects electrically interconnecting the contacts with the conductive elements.

17. The method of claim 16, wherein the step of depositing a conductive matrix material includes dispensing the conductive matrix material directly onto the microelectronic package.

18. The method of claim 16, wherein the step of depositing a conductive matrix material includes stenciling the conductive matrix material directly onto the microelectronic package.

19. The method of claim 16, wherein the step of depositing a conductive matrix material includes transfer printing the conductive matrix material directly onto the microelectronic package.

20. The method of claim 16, wherein the step of depositing a dielectric material includes covering the entire edge surface of the substrate.

21. The method of claim 20, wherein the step of depositing a dielectric material includes covering at least a portion of the second surface of the substrate.

22. The method of claim 16, wherein the step of depositing a dielectric material includes covering at least a portion of the second surface of the substrate.