Device with through-silicon via (TSV) and method of forming the same

• US 8,525,343 B2
• Filed: 09/28/2010
• Issued: 09/03/2013
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Tsang-Jiuh, Liao, Ebin
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US12/892,409
• Publication Number:
  US 20120074582A1
• Time in Patent Office: 1,071 Days
• Field of Search: 257/774, 257/E23.145, 257/760
• US Class Current: 257/774
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

A device with through-silicon via (TSV) and a method of forming the same includes the formation of an opening in a silicon substrate, the formation of a first insulation layer on the sidewalls and bottom of the opening, the formation of a second insulation layer on the sidewalls and bottom of the opening. A first interface between the first insulation layer and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm. A second interface between the second insulation layer and the conductive layer has an interface roughness with a peak-to-valley height less than 5 nm.

Claims

1. A device, comprising:

a silicon substrate having a first surface and a second surface opposite the first surface;

a through-silicon via (TSV) structure passing through the silicon substrate from the first surface to the second surface; and

an insulation structure formed between the silicon substrate and the TSV structure,

wherein a first interface between the insulation structure and the silicon substrate from the first surface to the second surface has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the TSV structure from the first surface to the second surface has an interface roughness with a peak-to-valley height less than 5 nm.

2. The device of claim 1, wherein the insulation structure comprises a first insulation layer adjacent to the silicon substrate, and a second insulation layer adjacent to the TSV structure.

3. The device of claim 2, wherein the second insulation layer has an isotropic etching rate in a diluted hydrofluoric acid solution greater than an isotropic etching rate of the first insulation layer in the diluted hydrofluoric acid solution.

4. The device of claim 2, wherein a third interface between the first insulation layer and the second insulation layer has an interface roughness with a peak-to-valley height greater than 10 nm.

5. The device of claim 2, wherein the first insulation layer is an oxide layer, and the second insulation layer is an oxide layer.

6. The device of claim 1, wherein the TSV structure comprises a copper layer.

7. The device of claim 6, wherein the TSV structure comprises a diffusion barrier layer surrounding the copper layer.

8. The device of claim 1, further comprising a first die electrically coupled to a first side of the silicon substrate.

9. The device of claim 8, further comprising a second die electrically coupled to a second side of the silicon substrate, opposite to the first side of the silicon substrate.

10. A three dimensional integrated circuit (3D-IC) comprising:

a first substrate having a first surface and a second surface opposite the first surface;

a through-silicon via (TSV) structure passing through the first substrate from the first surface to the second surface;

an insulation structure formed between the silicon substrate and the TSV structure,

wherein a first interface between the insulation structure and the silicon substrate from the first surface to the second surface has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the TSV structure from the first surface to the second surface has an interface roughness with a peak-to-valley height less than 5 nm; and

a second substrate electrically connected to the first substrate.

11. The 3D-IC of claim 10, wherein the insulation structure comprises a first insulation layer adjacent to the first substrate, and a second insulation layer adjacent to the TSV structure.

12. The 3D-IC of claim 11, wherein the second insulation layer has an isotropic etching rate in a diluted hydrofluoric acid solution greater than an isotropic etching rate of the first insulation layer in the diluted hydrofluoric acid solution.

13. The 3D-IC of claim 11, wherein a third interface between the first insulation layer and the second insulation layer has an interface roughness with a peak-to-valley height greater than 10 nm.

14. The 3D-IC of claim 10, further comprising:

a first die electrically coupled to a first side of the silicon substrate; and

a second die electrically coupled to a second side of the silicon substrate, opposite to the first side of the silicon substrate.

15. The 3D-IC of claim 14, further comprising an encapsulant over the first die.

16. The 3D-IC of claim 10, wherein the TSV structure comprises a copper layer and a diffusion barrier layer surrounding the copper layer.

17. The 3D-IC of claim 16, wherein the diffusion barrier layer comprises at least one of TaN, Ta, Ti, TiN, TiSiN or WN.

18. The 3D-IC of claim 10, wherein the insulation structure has a thickness ranging from about 50 nm to about 5 μ

m.

20. The device of claim 18, wherein a first interface between the insulation structure and the silicon substrate has an interface roughness with a peak-to-valley height less than 5 nm, and a second interface between the insulation structure and the TSV structure has an interface roughness with a peak-to-valley height less than 5 nm.

21. The device of claim 18, wherein the insulation structure has a thickness ranging from about 50 nm to about 5 μ

m.

19. A device, comprising:

a silicon substrate having a first surface and a second surface opposite the first surface;

a through-silicon via (TSV) structure passing through the silicon substrate from the first surface to the second surface; and

an insulation structure formed between the silicon substrate and the TSV structure,

wherein the insulation structure comprises a first insulating layer and a second insulating layer, and an interface between the first insulating layer and the second insulating layer from the first surface to the second surface has an interface roughness with a peak-to-valley height greater than 10 nm.