Trigger circuits and event counters for an IC

• US 8,525,548 B2
• Filed: 12/29/2008
• Issued: 09/03/2013
• Est. Priority Date: 08/04/2008
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad, Redgrave, Jason, Huang, Dai, Teig, Steven
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/057,477
• Publication Number:
  US 20110199117A1
• Time in Patent Office: 1,709 Days
• Field of Search: None
• US Class Current: 326/38
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06M 3/00 Counters with additional facilities generating electric pulses at random intervals H03K3/84
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Some embodiments provide an integrated circuit (‘IC’). The IC includes multiple configurable circuits that configurably perform operations of a user design based on configuration data. The IC also includes a configurable trigger circuit that receives a set of configuration data that specifies an operational event. The configurable trigger circuit also determines whether the operational event has occurred during implementation of the user design of the IC. Additionally, the operational trigger event outputs a trigger signal upon determining that the operational trigger event has occurred.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable circuits for configurably performing operations of a user design based on configuration data; and

a configurable trigger circuit for outputting a trigger signal upon determining that at least one of first and second operational trigger events has occurred, wherein the configurable trigger circuit determines whether the first operational trigger event has occurred during a first set of clock cycles and reconfigures to determine whether the second operational trigger event has occurred during a second set of clock cycles, wherein the reconfiguration occurs while the IC is performing the operations of the user design.

2. The IC of claim 1, wherein determining whether an operational trigger event has occurred comprises performing a comparison between user signals in the plurality of configurable circuits.

3. The IC of claim 2, wherein said comparison is a comparison of an m-bit variable to an n-bit variable, wherein m and n are two different integers.

4. The IC of claim 2, wherein said comparison comprises (i) a first comparison of an m-bit variable to an n-bit variable and (ii) a second comparison of an x-bit variable to a y-bit variable, wherein m, n, x, and y are integers, wherein m is different from x and y, wherein n is different from x and y.

5. The IC of claim 4, wherein said first and second comparisons occur within a same clock cycle.

6. The IC of claim 4, wherein said first comparison occurs within a first clock cycle and the second comparison occurs within a second different clock cycle.

15. The IC of claim 1, wherein each clock cycle of the first and second sets of clock cycles is a sub-cycle of a user clock cycle.

16. The IC of claim 1, wherein an operational trigger event occurs when a plurality of triggering conditions occur.

17. The IC of claim 16, wherein the plurality of triggering conditions are synchronous with each other.

18. The IC of claim 16, wherein the plurality of triggering conditions are nested.

7. An integrated circuit (“

IC”

) comprising;

a plurality of configurable circuits for configurably performing operations of a user design based on configuration data;

a trigger circuit for determining whether a plurality of operational events of the user design have occurred in the IC and, upon determining that the plurality of operational events have occurred, outputting a trigger signal that indicates that the plurality of operational events have occurred in the IC; and

a trace buffer for storing a set of user design values of the user design based on the trigger signal and a clock qualification signal that controllably defines a first set of clock cycles during which the trace buffer stores user design values and a second set of clock cycles during which the trace buffer does not store user design values.

8. The IC of claim 7, wherein a particular operational event is defined by a user.

9. The IC of claim 7, wherein the trigger circuit comprises a plurality of storage elements, each of the plurality of storage elements storing a value that indicates whether a particular operational event has occurred.

10. The IC of claim 7, wherein the trace buffer stores the set of user design values received within the first set of clock cycles after the trigger signal indicates that the plurality of operational events have occurred.

11. The IC of claim 7, wherein the trace buffer stores the set of user design values received within the first set of clock cycles until the trigger signal indicates that the plurality of operational events have occurred.

12. The IC of claim 7, wherein the trigger signal indicates that the plurality of operational events have occurred in a pre-defined sequence.

13. The IC of claim 7, wherein the IC is on a single substrate.

14. The IC of claim 7, wherein the IC is on a single IC die.

19. The IC of claim 7, wherein the first set of clock cycles occurs every N clock cycles, wherein N is an integer.

20. The IC of claim 7, wherein the first set of clock cycles comprises a plurality of consecutive clock cycles.