Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network

• US 8,525,569 B2
• Filed: 08/25/2011
• Issued: 09/03/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Pang, Liang-Teck, Restle, Phillip J., Bucelot, Thomas J.
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US13/217,335
• Publication Number:
  US 20130049827A1
• Time in Patent Office: 740 Days
• Field of Search: 327/295, 327/415, 327/565, 257/778, 257/777
• US Class Current: 327/293
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06531 Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10252 Germanium [Ge]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1531 the connection portion being formed only on the surface of the substrate opposite to the die mounting surface

Abstract

There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

Claims

1. A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata, the clock distribution network comprising:

on each of the two or more strata,

a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;

a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers; and

one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree;

wherein inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

2. The clock distribution network of claim 1, wherein the plurality of clock buffers comprise a plurality of sector clock buffers for driving the plurality of sectors and a plurality of relay clock buffers for distributing the global clock signals to the plurality of sector clock buffers.

3. The clock distribution network of claim 2, wherein the buffered clock tree on a given one of the two or more strata comprises a local clock divider for dividing the global clock signals provided to at least one of the plurality of relay clock buffers, at least one of the plurality of sector clock buffers, or at least one of the plurality of sectors.

4. The clock distribution network of claim 3, wherein the buffered clock tree on a different stratum with respect to the given one of the two or more strata comprises another local clock divider for dividing the global clock signals provided to at least one of the plurality of relay clock buffers, at least one of the plurality of sector clock buffers, or at least one of the plurality of sectors on the different stratum, and wherein the local clock divider comprises a divide-by-X circuit and the other local clock divider comprises a dummy delay circuit having a delay matched to that provided by the divide-by-X circuit, where X is an integer equal to or greater than one.

5. The clock distribution network of claim 1, wherein each of the one or more multiplexers provides respective ones of the global clock signals having a same phase or provides a same single clock source to the root on each of the two or more strata.

6. The clock distribution network of claim 1, wherein the clock grid on each of the two or more strata is shorted.

7. The clock distribution network of claim 1, wherein the plurality of multiplexers comprise at least one tri-state multiplexer or at least one static multiplexer.

8. A method for synchronizing global clock signals within a 3D chip stack having two or more strata, the method comprising:

providing on each of the two or more strata,

a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;

a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers; and

one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree;

shorting together inputs of at least some of the plurality of clock buffers on each of the two or more strata using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

9. The method of claim 8, further comprising shorting the clock grid on each of the two or more strata.

10. The method of claim 8, wherein only the inputs of the at least some of the plurality of clock buffers distributing the clock signals of a same phase are shorted together.

11. A clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata including a master stratum and non-master strata, the clock distribution network comprising:

on each of the two or more strata,

a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;

a multiple-level buffered clock tree having a plurality of sector clock buffers for driving the plurality of sectors, a plurality of relay clock buffers for distributing the global clock signals to the plurality of sector clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree; and

wherein the one or more multiplexers on the master stratum drive the one or more multiplexers on all of the non-master strata.

12. The clock distribution network of claim 11, wherein the master stratum is selectable.

13. The clock distribution network of claim 12, wherein each of the one or more multiplexers on the master stratum is configured to drive a same number of strata.

14. The clock distribution network of claim 11, wherein the one or more multiplexers comprise at least one tri-state multiplexer.

15. The clock distribution network of claim 14, wherein the at least one tri-state multiplexer on the master stratum is configured to drive all of the one or more multiplexers on all of the non-master strata.

16. The clock distribution network of claim 11, wherein portions of the clock grid on each of the two or more strata are shorted using chip-to-chip interconnects.

17. The clock distribution network of claim 11, wherein the master stratum is fixed, and each of the one or more multiplexers comprises a static CMOS multiplexer having two inputs and a single output.

18. The clock distribution network of claim 17, wherein portions of the buffered clock tree on at least one of the non-master strata are replicated on the master stratum and used to drive the one or more multiplexers on all of the non-master strata.

19. The clock distribution network of claim 11, wherein the master stratum includes two additional relay clock buffers in relation to the non-master strata, a first one of the two additional relay clock buffers being connected to one of the two inputs of the static CMOS multiplexer, a second one of the two additional relay clock buffers being connected to an input of the first one of the two additional relay clock buffers and being programmable for driving the non-master strata with a same delay as that provided by the first one of the two additional relay clock buffers.

20. A method for synchronizing global clock signals within a 3D chip stack having two or more strata, the method comprising:

providing on each of the two or more strata,

a clock grid having a plurality of sectors for providing the global clock signals to various chip locations;

a multiple-level buffered clock tree having a plurality of sector clock buffers for driving the plurality of sectors, a plurality of relay clock buffers for distributing the global clock signals to the plurality of sector clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree; and

driving the one or more multiplexers on all of the non-master strata using the one or more multiplexers on the master stratum.

21. The method of claim 20, wherein the master stratum is selectable.

22. The method of claim 21, wherein said driving step comprises configuring the one or more multiplexers in each of the two or more strata to drive a same number of strata.

23. The method of claim 20, wherein the one or more multiplexers comprise at least one tri-state multiplexer.

24. The method of claim 23, wherein said driving step comprises configuring the at least one tri-state multiplexer on the master stratum to drive all of the one or more multiplexers on all of the non-master strata.

25. The method of claim 20, further comprising shorting portions of the clock grid on each of the two or more strata using chip-to-chip interconnects.