Resistor thin film MTP memory

• US 8,526,214 B2
• Filed: 11/15/2011
• Issued: 09/03/2013
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Le Neel, Olivier
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US13/296,628
• Publication Number:
  US 20130121057A1
• Time in Patent Office: 658 Days
• Field of Search: 365/148, 365/218
• US Class Current: 365/148
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has two adjustable resistors and two heating elements. A dielectric material separates the heating elements from the adjustable resistors. One heating element alters the resistance of one of the resistors by applying heat thereto to write data to the memory cell. The other heating element alters the resistance of the other resistor by applying heat thereto to erase data from the memory cell.

Claims

1. A method comprising:

writing data to a memory cell having a first and a second thin film adjustable resistor, the writing including;

passing a first current through a first thin film heating element; and

altering a resistance of the first thin film adjustable resistor;

erasing data from the memory cell, including;

passing a second current through a second thin film heating element; and

altering a resistance of the second thin film adjustable resistor.

2. The method of claim 1 wherein altering the resistance of the first thin film adjustable resistor includes increasing a difference in the resistances of the first and second adjustable thin film resistors.

3. The method of claim 2 wherein prior to writing data to the memory cell the difference in the resistances between the first and second adjustable thin film resistors is substantially zero.

4. The method of claim 2 wherein altering the resistance of the second thin film resistor includes reducing a difference in the resistances of the first and second adjustable thin film resistor.

5. The method of claim 4 wherein reducing the resistance of the second thin film resistor includes making the resistances of the first and second thin film adjustable resistors substantially the same.

6. The method of claim 1 comprising reading data from the memory cell by comparing the resistance of the first thin film adjustable resistor to the resistance of the second thin film adjustable resistor.

7. The method of claim 6 wherein writing data to the memory cell comprises:

generating heat in the first heating element; and

conducting heat from the first heating element through the dielectric material to heat the first thin film adjustable resistor.

8. A method comprising:

altering a resistance of a first thin film resistor within a memory cell to write data to the memory cell; and

altering a resistance of a second thin film resistor within the memory cell to erase data from the memory cell.

9. The method of claim 8 wherein writing data to the memory cell comprises increasing a difference in the resistance of the first thin film resistor and the second thin film resistor.

10. The method of claim 9 wherein erasing data to the memory cell comprises reducing a difference between the resistance of the first thin film resistor and the second thin film resistor.

11. The method of claim 8 comprising reading data from the memory cell by comparing the resistance of the first thin film resistor to the resistance of the second thin film resistor.

12. The method of claim 9 wherein reading data from the memory cell comprises:

passing a current through the first and second thin film resistors, the first and second thin film resistors being connected in series at an intermediate node; and

comparing a voltage from the intermediate node to a reference voltage.

13. The method of claim 8 comprising writing data to the memory cell further altering a resistance of the first thin film resistor after erasing data from the memory cell.