Enhanced static random access memory stability using asymmetric access transistors and design structure for same

• US 8,526,219 B2
• Filed: 02/07/2012
• Issued: 09/03/2013
• Est. Priority Date: 01/22/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bansal, Aditya, Chuang, Ching-Te K., Kim, Jae-Joon, Lo, Shih-Hsien, Rao, Rahul M.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/367,495
• Publication Number:
  US 20120185817A1
• Time in Patent Office: 574 Days
• Field of Search: 365/154, 365/156, 365/189.09
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.

Claims

1. A design structure embodied in a machine readable medium, said design structure comprising a memory circuit, said memory circuit comprising:

a plurality of bit line structures, each of said bit line structures comprising a true bit line and a complementary bit line;

a plurality of word lines structures intersecting said plurality of bit line structures to form a plurality of cell locations; and

a plurality of cells located at said plurality of cell locations, each of said cells comprising;

a logical storage element;

a first access transistor selectively coupling a given one of said true bit lines to said logical storage element, wherein a current from said logical storage element to said given one of said true bit lines is higher than a current from said given one of said true bit lines to said logical storage element; and

a second access transistor selectively coupling a corresponding given one of said complementary bit lines to said logical storage element, wherein a current from said logical storage element to said corresponding given one of said complementary bit lines is higher than a current from said corresponding given one of said complementary bit lines to said logical storage element;

wherein at least one of said first and second access transistors comprises an asymmetric access transistor configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins.

2. The design structure of claim 1, wherein said logical storage element comprises a storage flip-flop, said storage flip-flop comprising:

a first inverter; and

a second inverter cross-coupled to said first inverter to form said storage flip-flop.

3. The design structure of claim 2, wherein said first and second access transistors comprise metal oxide semiconductor field effect transistors.

4. The design structure of claim 1, wherein said design structure comprises a netlist.

5. The design structure of claim 1, wherein said design structure resides on storage medium as a data format used for exchange of layout data of integrated circuits.