Processor with memory delayed bit line precharging

• US 8,526,257 B2
• Filed: 10/22/2012
• Issued: 09/03/2013
• Est. Priority Date: 10/13/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Su, Jason T., Sheu, Jason, Tjeng, Jensen, Chen, Hong-Yi
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): REIDLINGER, RONALD LANCE
• Application Number:
  US13/657,502
• Publication Number:
  US 20130044555A1
• Time in Patent Office: 316 Days
• Field of Search: 365/203, 365/233.1, 365/233.11, 365/125, 365/205
• US Class Current: 365/203
• CPC Class Codes: G06F 12/0882 Page mode
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 2207/2281 Timing of a read operation
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array.

Claims

1. A processor comprising:

a memory comprising an array of memory cells;

a control module configured to (i) generate a clock signal at a first rate, (ii) reduce the first rate of the clock signal to a second rate for a predetermined period, and (iii) adjust the clock signal from the second rate back to the first rate at an end of the predetermined period;

a precharge circuit configured to (i) based on the clock signal at the first rate, precharge first bit lines connected to memory cells in a first row of the array of memory cells, (ii) based on the clock signal at the second rate, refrain from precharging the first bit lines during the predetermined period, and (iii) precharge the first bit lines subsequent to the end of the predetermined period; and

an amplifier module configured to (i) based on the clock signal at the first rate, access first instructions stored in the first row of the array of memory cells, and (ii) based on the clock signal at the second rate, access second instructions stored in the first row of the array of memory cells or in a second row of the array of memory cells.

2. The processor of claim 1, wherein:

the precharge circuit is configured to (i) during a first precharge event, precharge the first bit lines based on the clock signal at the first rate to provide a first amount of bit line separation for accessing the first instructions, and (ii) during a second precharge event, precharge the first bit lines based on the clock signal at the second rate to provide a second amount of bit line separation for accessing the second instructions; and

the amplifier module is configured to

access the first instructions (i) subsequent to the first precharge event, and (ii) prior to the second precharge event, and

access the second instructions subsequent to the second precharge event.

3. The processor of claim 2, wherein:

the first precharge event is performed a first period after a previous precharge event;

the second precharge event is performed a second period after the first precharge event;

the second period is longer than the first period;

the first precharge event is performed consecutively after the previous precharge event; and

the second precharge event is performed consecutively after the first precharge event.

4. The processor of claim 2, wherein:

during the first precharge event, a first voltage potential of a first one of the first bit lines is equal to a second voltage potential of a second one of the first bit lines;

subsequent to the first precharge event, a difference between the first voltage potential and the second voltage potential increases;

the first voltage potential remains different than the second voltage potential for a separation period between the first precharge event and the second precharge event; and

a duration of the separation period is based on the second rate.

5. The processor of claim 2, wherein:

the first bit lines include a first line and a second line;

during the first precharge event, an amount of bit line separation between the first line and the second line is zero;

the amount of bit line separation between the first line and the second line is greater than zero subsequent to the first precharge event;

the amount of bit line separation between the first line and the second line remains greater than zero for a separation period between the first precharge event and the second precharge event;

a duration of the separation period is based on the second rate; and

the amount of bit line separation between the first line and the second line is equal to zero during the second precharge event.

6. The processor of claim 2, wherein the control module is configured to reduce the first rate of the clock signal to the second rate during the first precharge event.

7. The processor of claim 1, wherein the precharge circuit is configured to:

based on the clock signal at the first rate, precharge the first bit lines during a first cycle of the clock signal;

refrain from precharging the first bit lines during a second cycle of the clock signal, wherein the second cycle occurs consecutively after the first cycle of the clock signal; and

based on the clock signal at the second rate, precharge the first bit lines during a third cycle of the clock signal, wherein the third cycle of the clock signal occurs consecutively after the second cycle of the clock signal.

8. The processor of claim 7, wherein the first rate of the clock signal is reduced to the second rate during the second cycle of the clock signal.

9. The processor of claim 1, further comprising a decoder configured to (i) generate a first pulse on a word line signal to access the first instructions, and (ii) generate a second pulse on the word line signal to access second instructions,

wherein the amplifier module is configured to (i) access the first instructions based on the first pulse of the word line signal, and (ii) access the second instructions based on the second pulse of the word line signal.

10. The processor of claim 9, wherein:

the first pulse of the word line signal is generated during a first cycle of the clock signal;

the second pulse of the word line signal is generated during a second cycle of the clock signal; and

the second cycle of the clock signal occurs consecutively after the first cycle of the clock signal.

11. The processor of claim 9, wherein the precharge circuit is configured to:

precharge the first bit lines to access the first instructions a first period after a first falling edge of the first pulse of the word line signal; and

precharge the first bit lines to access the second instructions a second period after a second falling edge of the second pulse of the word line signal,

wherein

a first cycle of the word line signal includes the first pulse of the word line signal,

a second cycle of the word line signal includes the second pulse of the word line signal,

the second cycle is generated consecutively after the first cycle, and

the second period is longer than the first period.

12. The processor of claim 9, wherein:

the word line signal defines a period to increase separation between two of the first bit lines; and

the decoder is configured to, based on a predetermined number of read cycles, set the period defined to increase separation between the two of the first bit lines.

13. The processor of claim 9, wherein:

the control module is configured to generate a third pulse on the word line signal to access third instructions stored in the second row of the array of memory cells;

the precharge circuit is configured to, prior to the amplifier module accessing the third instructions, precharge second bit lines connected to memory cells in the second row of the array of the memory cells, wherein the second bit lines are different than the first bit lines; and

the amplifier module is configured to access the third instructions based on the third pulse.

14. The processor of claim 9, wherein the control module is configured to:

determine bit line separation based on a number of access cycles to be performed along the word line; and

precharge the first bit lines to provide bit line separation when accessing the first instructions and the second instructions.

15. A method comprising:

generating a clock signal at a first rate;

reducing the first rate of the clock signal to a second rate for a predetermined period;

adjusting the clock signal from the second rate back to the first rate at an end of the predetermined period;

based on the clock signal at the first rate, precharging first bit lines connected to memory cells in a first row of an array of memory cells;

based on the clock signal at the second rate, refraining from precharging the first bit lines during the predetermined period;

precharging the first bit lines subsequent to the end of the predetermined period;

based on the clock signal at the first rate, accessing first instructions stored in the first row of the array of memory cells; and

based on the clock signal at the second rate, accessing second instructions stored in the first row of the array of memory cells or in a second row of the array of memory cells.

16. The method of claim 15, further comprising:

during a first precharge event, precharging the first bit lines based on the clock signal at the first rate to provide a first amount of bit line separation for accessing the first instructions;

during a second precharge event, precharging the first bit lines based on the clock signal at the second rate to provide a second amount of bit line separation for accessing the second instructions;

accessing the first instructions (i) subsequent to the first precharge event, and (ii) prior to the second precharge event; and

accessing the second instructions subsequent to the second precharge event.

17. The method of claim 16, wherein:

the first bit lines include a first line and a second line;

during the first precharge event, an amount of bit line separation between the first line and the second line is zero;

the amount of bit line separation between the first line and the second line is greater than zero subsequent to the first precharge event;

the amount of bit line separation between the first line and the second line remains greater than zero for a separation period between the first precharge event and the second precharge event;

a duration of the separation period is based on the second rate; and

the amount of bit line separation between the first line and the second line is equal to zero during the second precharge event.

18. The method of claim 15, further comprising:

based on the clock signal at the first rate, precharging the first bit lines during a first cycle of the clock signal;

refraining from precharging the first bit lines during a second cycle of the clock signal, wherein the second cycle occurs consecutively after the first cycle of the clock signal; and

based on the clock signal at the second rate, precharging the first bit lines during a third cycle of the clock signal, wherein the third cycle of the clock signal occurs consecutively after the second cycle of the clock signal.

19. The method of claim 15, further comprising:

generating a first pulse on a word line signal to access the first instructions;

generating a second pulse on the word line signal to access second instructions;

accessing the first instructions based on the first pulse of the word line signal; and

accessing the second instructions based on the second pulse of the word line signal.

20. The method of claim 19, further comprising:

precharging the first bit lines to access the first instructions a first period after a first falling edge of the first pulse of the word line signal; and

precharging the first bit lines to access the second instructions a second period after a second falling edge of the second pulse of the word line signal,

wherein

a first cycle of the word line signal includes the first pulse of the word line signal,

a second cycle of the word line signal includes the second pulse of the word line signal,

the second cycle is generated consecutively after the first cycle, and

the second period is longer than the first period.